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Hyun Nam

Examiner (ID: 14863, Phone: (571)270-1725 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184, 2183
Total Applications
1039
Issued Applications
880
Pending Applications
63
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19878654 [patent_doc_number] => 20250110911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => I/O CARRIER AND BACKPLANE FOR INDUSTRIAL PROCESS CONTROL SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/891841 [patent_app_country] => US [patent_app_date] => 2024-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18891841 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/891841
I/O CARRIER AND BACKPLANE FOR INDUSTRIAL PROCESS CONTROL SYSTEMS Sep 19, 2024 Pending
Array ( [id] => 19787398 [patent_doc_number] => 20250061077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => MEMORY EXPANDER, COMPUTING SYSTEMS, AND OPERATING METHOD OF THE HOST DEVICE [patent_app_type] => utility [patent_app_number] => 18/797821 [patent_app_country] => US [patent_app_date] => 2024-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18797821 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/797821
MEMORY EXPANDER, COMPUTING SYSTEMS, AND OPERATING METHOD OF THE HOST DEVICE Aug 7, 2024 Pending
Array ( [id] => 19787386 [patent_doc_number] => 20250061065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => CONFIGURING PCI EXPRESS MODULE USING HARDWARE IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/781989 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781989 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781989
CONFIGURING PCI EXPRESS MODULE USING HARDWARE IN A MEMORY SUB-SYSTEM Jul 22, 2024 Pending
Array ( [id] => 20273452 [patent_doc_number] => 12443232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Port replicator [patent_app_type] => utility [patent_app_number] => 18/772379 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 5301 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772379 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772379
Port replicator Jul 14, 2024 Issued
Array ( [id] => 20273452 [patent_doc_number] => 12443232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Port replicator [patent_app_type] => utility [patent_app_number] => 18/772379 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 5301 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772379 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772379
Port replicator Jul 14, 2024 Issued
Array ( [id] => 19514294 [patent_doc_number] => 20240345980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => Chip Management Apparatus and Related Method [patent_app_type] => utility [patent_app_number] => 18/748324 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18748324 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/748324
Chip Management Apparatus and Related Method Jun 19, 2024 Pending
Array ( [id] => 19499311 [patent_doc_number] => 20240338329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => INTEGRATED CIRCUIT GENERATION WITH IMPROVED INTERCONNECT [patent_app_type] => utility [patent_app_number] => 18/747410 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747410 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/747410
INTEGRATED CIRCUIT GENERATION WITH IMPROVED INTERCONNECT Jun 17, 2024 Pending
Array ( [id] => 19451187 [patent_doc_number] => 20240311317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => MEMORY SYSTEM WITH ADAPTIVE REFRESH [patent_app_type] => utility [patent_app_number] => 18/674138 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674138 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674138
MEMORY SYSTEM WITH ADAPTIVE REFRESH May 23, 2024 Pending
Array ( [id] => 19451187 [patent_doc_number] => 20240311317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => MEMORY SYSTEM WITH ADAPTIVE REFRESH [patent_app_type] => utility [patent_app_number] => 18/674138 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674138 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674138
MEMORY SYSTEM WITH ADAPTIVE REFRESH May 23, 2024 Pending
Array ( [id] => 19405621 [patent_doc_number] => 20240289132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => PROGRAMMATICALLY CONTROLLED DATA MULTICASTING ACROSS MULTIPLE COMPUTE ENGINES [patent_app_type] => utility [patent_app_number] => 18/660763 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660763 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660763
PROGRAMMATICALLY CONTROLLED DATA MULTICASTING ACROSS MULTIPLE COMPUTE ENGINES May 9, 2024 Pending
Array ( [id] => 20273626 [patent_doc_number] => 12443408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Processing pipeline with zero loop overhead [patent_app_type] => utility [patent_app_number] => 18/647891 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6899 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647891 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647891
Processing pipeline with zero loop overhead Apr 25, 2024 Issued
Array ( [id] => 20273626 [patent_doc_number] => 12443408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Processing pipeline with zero loop overhead [patent_app_type] => utility [patent_app_number] => 18/647891 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6899 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647891 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647891
Processing pipeline with zero loop overhead Apr 25, 2024 Issued
Array ( [id] => 19514293 [patent_doc_number] => 20240345979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => NETWORK INTERFACE DEVICE [patent_app_type] => utility [patent_app_number] => 18/642714 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642714 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/642714
NETWORK INTERFACE DEVICE Apr 21, 2024 Pending
Array ( [id] => 19383179 [patent_doc_number] => 20240273049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => COMPUTING SYSTEM, ADDRESSING METHOD, COMPUTE NODE, STORAGE MEDIUM, AND PROGRAM PRODUCT [patent_app_type] => utility [patent_app_number] => 18/641106 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641106 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/641106
COMPUTING SYSTEM, ADDRESSING METHOD, COMPUTE NODE, STORAGE MEDIUM, AND PROGRAM PRODUCT Apr 18, 2024 Pending
Array ( [id] => 19558602 [patent_doc_number] => 20240370394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => DEVICE AND METHODS FOR COMMUNICATION BETWEEN ELECTRONIC COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/632143 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632143 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/632143
Device and methods for communication between electronic components Apr 9, 2024 Issued
Array ( [id] => 19362922 [patent_doc_number] => 20240264956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => EFFICIENT QUEUE ACCESS FOR USER-SPACE PACKET PROCESSING [patent_app_type] => utility [patent_app_number] => 18/624661 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624661 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624661
EFFICIENT QUEUE ACCESS FOR USER-SPACE PACKET PROCESSING Apr 1, 2024 Pending
Array ( [id] => 19482185 [patent_doc_number] => 20240330227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => COMMUNICATION SYSTEM AND COMMUNICATION METHOD [patent_app_type] => utility [patent_app_number] => 18/620244 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/620244
COMMUNICATION SYSTEM AND COMMUNICATION METHOD Mar 27, 2024 Pending
Array ( [id] => 20281944 [patent_doc_number] => 20250307186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => INTERRUPT COALESCING DURING PROCESSOR IDLE [patent_app_type] => utility [patent_app_number] => 18/620719 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620719 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/620719
INTERRUPT COALESCING DURING PROCESSOR IDLE Mar 27, 2024 Pending
Array ( [id] => 19466341 [patent_doc_number] => 20240320011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => Pipelined Processor Architecture with Configurable Grouping of Processor Elements [patent_app_type] => utility [patent_app_number] => 18/612608 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612608 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612608
Pipelined Processor Architecture with Configurable Grouping of Processor Elements Mar 20, 2024 Pending
Array ( [id] => 19466341 [patent_doc_number] => 20240320011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => Pipelined Processor Architecture with Configurable Grouping of Processor Elements [patent_app_type] => utility [patent_app_number] => 18/612608 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612608 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612608
Pipelined Processor Architecture with Configurable Grouping of Processor Elements Mar 20, 2024 Pending
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