Search

Hyun Nam

Examiner (ID: 9154, Phone: (571)270-1725 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184, 2183
Total Applications
1040
Issued Applications
882
Pending Applications
59
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18119299 [patent_doc_number] => 11550694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Packet backpressure detection method, apparatus, and device [patent_app_type] => utility [patent_app_number] => 16/653326 [patent_app_country] => US [patent_app_date] => 2019-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 13049 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16653326 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/653326
Packet backpressure detection method, apparatus, and device Oct 14, 2019 Issued
Array ( [id] => 15836769 [patent_doc_number] => 20200133667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => MICROCONTROLLER CAPABLE TO EXECUTE A CONFIGURABLE PROCESSING IN AN ACCELERATED MANNER [patent_app_type] => utility [patent_app_number] => 16/599523 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599523 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599523
MICROCONTROLLER CAPABLE TO EXECUTE A CONFIGURABLE PROCESSING IN AN ACCELERATED MANNER Oct 10, 2019 Abandoned
Array ( [id] => 16764180 [patent_doc_number] => 20210109761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => Datapath Circuitry for Math Operations using SIMD Pipelines [patent_app_type] => utility [patent_app_number] => 16/597625 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597625 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/597625
Datapath circuitry for math operations using SIMD pipelines Oct 8, 2019 Issued
Array ( [id] => 16651960 [patent_doc_number] => 10929137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Arithmetic processing device and control method for arithmetic processing device [patent_app_type] => utility [patent_app_number] => 16/597410 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10142 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597410 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/597410
Arithmetic processing device and control method for arithmetic processing device Oct 8, 2019 Issued
Array ( [id] => 16729714 [patent_doc_number] => 20210096861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => SYSTEM AND METHOD TO PREFETCH POINTER BASED STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/589706 [patent_app_country] => US [patent_app_date] => 2019-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16589706 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/589706
SYSTEM AND METHOD TO PREFETCH POINTER BASED STRUCTURES Sep 30, 2019 Abandoned
Array ( [id] => 16729724 [patent_doc_number] => 20210096871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => MERGE EXECUTION UNIT FOR MICROINSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/589527 [patent_app_country] => US [patent_app_date] => 2019-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16589527 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/589527
Merge execution unit for microinstructions Sep 30, 2019 Issued
Array ( [id] => 17331385 [patent_doc_number] => 11221848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Sharing register file usage between fused processing resources [patent_app_type] => utility [patent_app_number] => 16/582406 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 37 [patent_no_of_words] => 29149 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582406 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582406
Sharing register file usage between fused processing resources Sep 24, 2019 Issued
Array ( [id] => 17394752 [patent_doc_number] => 11243766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Flexible instruction set disabling [patent_app_type] => utility [patent_app_number] => 16/582701 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 20872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582701 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582701
Flexible instruction set disabling Sep 24, 2019 Issued
Array ( [id] => 15772891 [patent_doc_number] => 20200117463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => CACHE CONTROL CIRCUITRY AND METHODS [patent_app_type] => utility [patent_app_number] => 16/580158 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580158 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/580158
Cache control circuitry and methods Sep 23, 2019 Issued
Array ( [id] => 15367521 [patent_doc_number] => 20200019525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => MEMORY ACCESS OPTIMIZATION FOR AN I/O ADAPTER IN A PROCESSOR COMPLEX [patent_app_type] => utility [patent_app_number] => 16/578721 [patent_app_country] => US [patent_app_date] => 2019-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578721 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/578721
Memory access optimization for an I/O adapter in a processor complex Sep 22, 2019 Issued
Array ( [id] => 16772697 [patent_doc_number] => 10983801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Load/store ordering violation management [patent_app_type] => utility [patent_app_number] => 16/562675 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 12102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562675 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/562675
Load/store ordering violation management Sep 5, 2019 Issued
Array ( [id] => 15257929 [patent_doc_number] => 20190377698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => In-Connector Data Storage Device [patent_app_type] => utility [patent_app_number] => 16/547462 [patent_app_country] => US [patent_app_date] => 2019-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547462 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547462
In-connector data storage device Aug 20, 2019 Issued
Array ( [id] => 16667074 [patent_doc_number] => 10936320 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-02 [patent_title] => Efficient performance of inner loops on a multi-lane processor [patent_app_type] => utility [patent_app_number] => 16/543540 [patent_app_country] => US [patent_app_date] => 2019-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7450 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543540 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/543540
Efficient performance of inner loops on a multi-lane processor Aug 16, 2019 Issued
Array ( [id] => 15714735 [patent_doc_number] => 20200104134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => COMPUTING 2-BODY STATISTICS ON GRAPHICS PROCESSING UNITS (GPUs) [patent_app_type] => utility [patent_app_number] => 16/521852 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521852 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521852
Computing 2-body statistics on graphics processing units (GPUs) Jul 24, 2019 Issued
Array ( [id] => 16201010 [patent_doc_number] => 10726177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Reconfigurable interconnect [patent_app_type] => utility [patent_app_number] => 16/517371 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 32755 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517371 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517371
Reconfigurable interconnect Jul 18, 2019 Issued
Array ( [id] => 17744445 [patent_doc_number] => 11392514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Data processing apparatus having multiple processors and multiple interfaces [patent_app_type] => utility [patent_app_number] => 17/280572 [patent_app_country] => US [patent_app_date] => 2019-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4128 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17280572 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/280572
Data processing apparatus having multiple processors and multiple interfaces Jul 17, 2019 Issued
Array ( [id] => 17209577 [patent_doc_number] => 11169950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Method for controlling serial port information of server host [patent_app_type] => utility [patent_app_number] => 16/509758 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2086 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16509758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/509758
Method for controlling serial port information of server host Jul 11, 2019 Issued
Array ( [id] => 15500773 [patent_doc_number] => 20200050575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => FLEXIBLE PROTOCOL AND ASSOCIATED HARDWARE FOR ONE-WIRE RADIO FREQUENCY FRONT-END INTERFACE [patent_app_type] => utility [patent_app_number] => 16/509957 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16509957 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/509957
Flexible protocol and associated hardware for one-wire radio frequency front-end interface Jul 11, 2019 Issued
Array ( [id] => 15027311 [patent_doc_number] => 20190324660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/503200 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503200 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503200
Semiconductor device and operating method thereof Jul 2, 2019 Issued
Array ( [id] => 15120929 [patent_doc_number] => 20190347097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => DIGITAL SIGNAL PROCESSING ARRAY USING INTEGRATED PROCESSING ELEMENTS [patent_app_type] => utility [patent_app_number] => 16/503447 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503447 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503447
Digital signal processing array using integrated processing elements Jul 2, 2019 Issued
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