Hyun Nam

Array ( [id] => 17084064 [patent_doc_number] => 20210279070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => SNAPSHOT TRANSMISSION FROM STORAGE ARRAY TO CLOUD USING MULTI-PATH INPUT-OUTPUT [patent_app_type] => utility [patent_app_number] => 16/811751 [patent_app_country] => US [patent_app_date] => 2020-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16811751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16240299 [patent_doc_number] => 20200257533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => PROCESSOR AND INSTRUCTION EXECUTION METHOD [patent_app_type] => utility [patent_app_number] => 16/786191 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16178982 [patent_doc_number] => 20200225950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => MODE-SPECIFIC ENDBRANCH FOR CONTROL FLOW TERMINATION [patent_app_type] => utility [patent_app_number] => 16/741498 [patent_app_country] => US [patent_app_date] => 2020-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17528567 [patent_doc_number] => 11301255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Method, apparatus, device, and storage medium for performing processing task [patent_app_type] => utility [patent_app_number] => 16/729989 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6874 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729989 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16212501 [patent_doc_number] => 20200245491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => HOT-PLUGGABLE CONNECTION FOR DATA COMMUNICATIONS [patent_app_type] => utility [patent_app_number] => 16/726577 [patent_app_country] => US [patent_app_date] => 2019-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16726577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17252997 [patent_doc_number] => 11188486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Master chip, slave chip, and inter-chip DMA transmission system [patent_app_type] => utility [patent_app_number] => 16/697122 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9751 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16780121 [patent_doc_number] => 20210117200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => CONTROLLING THE OPERATION OF A DECOUPLED ACCESS-EXECUTE PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/658494 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19718942 [patent_doc_number] => 12204479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Network-on-chip data processing method and device [patent_app_type] => utility [patent_app_number] => 17/278812 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 71 [patent_figures_cnt] => 71 [patent_no_of_words] => 68210 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17278812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18119299 [patent_doc_number] => 11550694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Packet backpressure detection method, apparatus, and device [patent_app_type] => utility [patent_app_number] => 16/653326 [patent_app_country] => US [patent_app_date] => 2019-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 13049 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16653326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15836769 [patent_doc_number] => 20200133667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => MICROCONTROLLER CAPABLE TO EXECUTE A CONFIGURABLE PROCESSING IN AN ACCELERATED MANNER [patent_app_type] => utility [patent_app_number] => 16/599523 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16764180 [patent_doc_number] => 20210109761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => Datapath Circuitry for Math Operations using SIMD Pipelines [patent_app_type] => utility [patent_app_number] => 16/597625 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16651960 [patent_doc_number] => 10929137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Arithmetic processing device and control method for arithmetic processing device [patent_app_type] => utility [patent_app_number] => 16/597410 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10142 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16729714 [patent_doc_number] => 20210096861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => SYSTEM AND METHOD TO PREFETCH POINTER BASED STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/589706 [patent_app_country] => US [patent_app_date] => 2019-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16589706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16729724 [patent_doc_number] => 20210096871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => MERGE EXECUTION UNIT FOR MICROINSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/589527 [patent_app_country] => US [patent_app_date] => 2019-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16589527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17331385 [patent_doc_number] => 11221848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Sharing register file usage between fused processing resources [patent_app_type] => utility [patent_app_number] => 16/582406 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 37 [patent_no_of_words] => 29149 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17394752 [patent_doc_number] => 11243766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Flexible instruction set disabling [patent_app_type] => utility [patent_app_number] => 16/582701 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 20872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15772891 [patent_doc_number] => 20200117463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => CACHE CONTROL CIRCUITRY AND METHODS [patent_app_type] => utility [patent_app_number] => 16/580158 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15367521 [patent_doc_number] => 20200019525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => MEMORY ACCESS OPTIMIZATION FOR AN I/O ADAPTER IN A PROCESSOR COMPLEX [patent_app_type] => utility [patent_app_number] => 16/578721 [patent_app_country] => US [patent_app_date] => 2019-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16772697 [patent_doc_number] => 10983801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Load/store ordering violation management [patent_app_type] => utility [patent_app_number] => 16/562675 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 12102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15257929 [patent_doc_number] => 20190377698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => In-Connector Data Storage Device [patent_app_type] => utility [patent_app_number] => 16/547462 [patent_app_country] => US [patent_app_date] => 2019-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547462 [rel_patent_id] =>[rel_patent_doc_number] =>)