Search

Hyun Nam

Examiner (ID: 9154, Phone: (571)270-1725 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184, 2183
Total Applications
1040
Issued Applications
882
Pending Applications
59
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15412693 [patent_doc_number] => 20200026669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/367700 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16367700 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/367700
Memory system Mar 27, 2019 Issued
Array ( [id] => 15412693 [patent_doc_number] => 20200026669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/367700 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16367700 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/367700
Memory system Mar 27, 2019 Issued
Array ( [id] => 15412693 [patent_doc_number] => 20200026669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/367700 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16367700 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/367700
Memory system Mar 27, 2019 Issued
Array ( [id] => 15248463 [patent_doc_number] => 10509756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Circuit device, electronic device, and cable harness [patent_app_type] => utility [patent_app_number] => 16/367485 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 18560 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16367485 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/367485
Circuit device, electronic device, and cable harness Mar 27, 2019 Issued
Array ( [id] => 15027851 [patent_doc_number] => 20190324930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => METHOD, DEVICE AND COMPUTER PROGRAM PRODUCT FOR ENABLING SR-IOV FUNCTIONS IN ENDPOINT DEVICE [patent_app_type] => utility [patent_app_number] => 16/298431 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16298431 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/298431
Method, device and computer program product for enabling SR-IOV functions in endpoint device Mar 10, 2019 Issued
Array ( [id] => 14872695 [patent_doc_number] => 20190286589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => APPARATUS AND METHOD TO IMPROVE PERFORMANCE IN DMA TRANSFER OF DATA [patent_app_type] => utility [patent_app_number] => 16/296946 [patent_app_country] => US [patent_app_date] => 2019-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16296946 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/296946
Apparatus and method to improve performance in DMA transfer of data Mar 7, 2019 Issued
Array ( [id] => 16772840 [patent_doc_number] => 10983948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Reconfigurable computing appliance [patent_app_type] => utility [patent_app_number] => 16/295058 [patent_app_country] => US [patent_app_date] => 2019-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2623 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16295058 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/295058
Reconfigurable computing appliance Mar 6, 2019 Issued
Array ( [id] => 16592473 [patent_doc_number] => 10901735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Apparatus and method to improve performance of memory accesses from plural arithmetic processors [patent_app_type] => utility [patent_app_number] => 16/295450 [patent_app_country] => US [patent_app_date] => 2019-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12765 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16295450 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/295450
Apparatus and method to improve performance of memory accesses from plural arithmetic processors Mar 6, 2019 Issued
Array ( [id] => 15854953 [patent_doc_number] => 10642762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => High capacity memory system with improved command-address and chip-select signaling mode [patent_app_type] => utility [patent_app_number] => 16/290346 [patent_app_country] => US [patent_app_date] => 2019-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 76 [patent_no_of_words] => 31795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16290346 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/290346
High capacity memory system with improved command-address and chip-select signaling mode Feb 28, 2019 Issued
Array ( [id] => 14750421 [patent_doc_number] => 20190258384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => HAPTICALLY ENHANCED INTERACTIVITY WITH INTERACTIVE CONTENT [patent_app_type] => utility [patent_app_number] => 16/284645 [patent_app_country] => US [patent_app_date] => 2019-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16284645 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/284645
Haptically enhanced interactivity with interactive content Feb 24, 2019 Issued
Array ( [id] => 16758492 [patent_doc_number] => 10977040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Heuristic invalidation of non-useful entries in an array [patent_app_type] => utility [patent_app_number] => 16/279052 [patent_app_country] => US [patent_app_date] => 2019-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8814 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16279052 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/279052
Heuristic invalidation of non-useful entries in an array Feb 18, 2019 Issued
Array ( [id] => 16751527 [patent_doc_number] => 20210103536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => PROGRAMMABLE COMPUTER IO DEVICE INTERFACE [patent_app_type] => utility [patent_app_number] => 16/971898 [patent_app_country] => US [patent_app_date] => 2019-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16971898 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/971898
Programmable computer IO device interface Feb 18, 2019 Issued
Array ( [id] => 16255516 [patent_doc_number] => 20200264890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => DIGIT VALIDATION CHECK CONTROL IN INSTRUCTION EXECUTION [patent_app_type] => utility [patent_app_number] => 16/277486 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16277486 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/277486
Digit validation check control in instruction execution Feb 14, 2019 Issued
Array ( [id] => 17283027 [patent_doc_number] => 11200056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Parallel union control device, parallel union control method, and storage medium [patent_app_type] => utility [patent_app_number] => 16/967866 [patent_app_country] => US [patent_app_date] => 2019-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16967866 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/967866
Parallel union control device, parallel union control method, and storage medium Feb 4, 2019 Issued
Array ( [id] => 14656663 [patent_doc_number] => 20190235460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => INTERRUPT EXCEPTION WINDOW PROTOCOL ON A DATA COMMUNICATION BUS AND METHODS AND APPARATUSES FOR USING SAME [patent_app_type] => utility [patent_app_number] => 16/264244 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16264244 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/264244
Interrupt exception window protocol on a data communication bus and methods and apparatuses for using same Jan 30, 2019 Issued
Array ( [id] => 17394754 [patent_doc_number] => 11243768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Mechanism for saving and retrieving micro-architecture context [patent_app_type] => utility [patent_app_number] => 16/259880 [patent_app_country] => US [patent_app_date] => 2019-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 8139 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16259880 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/259880
Mechanism for saving and retrieving micro-architecture context Jan 27, 2019 Issued
Array ( [id] => 14314383 [patent_doc_number] => 20190146895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => PACKET BACKPRESSURE DETECTION METHOD, APPARATUS, AND DEVICE [patent_app_type] => utility [patent_app_number] => 16/250168 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16250168 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/250168
Packet backpressure detection method, apparatus, and device Jan 16, 2019 Issued
Array ( [id] => 18119671 [patent_doc_number] => 11551066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Deep neural networks (DNN) hardware accelerator and operation method thereof [patent_app_type] => utility [patent_app_number] => 16/248042 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5961 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16248042 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/248042
Deep neural networks (DNN) hardware accelerator and operation method thereof Jan 14, 2019 Issued
Array ( [id] => 15386783 [patent_doc_number] => 10534576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Optimization apparatus and control method thereof [patent_app_type] => utility [patent_app_number] => 16/248028 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11769 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16248028 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/248028
Optimization apparatus and control method thereof Jan 14, 2019 Issued
Array ( [id] => 14314465 [patent_doc_number] => 20190146936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => DYNAMICALLY REMAPPING IN-PROCESS DATA TRANSFERS [patent_app_type] => utility [patent_app_number] => 16/243936 [patent_app_country] => US [patent_app_date] => 2019-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4799 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16243936 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/243936
Dynamically remapping in-process data transfers Jan 8, 2019 Issued
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