Hyun Nam

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Array ( [id] => 20358737 [patent_doc_number] => 12474730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Deserializer and memory module including the same [patent_app_type] => utility [patent_app_number] => 18/418856 [patent_app_country] => US [patent_app_date] => 2024-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 2463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418856 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19159779 [patent_doc_number] => 20240152486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => Reconfigurable Processor Circuit Architecture [patent_app_type] => utility [patent_app_number] => 18/415958 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 53892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20101830 [patent_doc_number] => 20250231766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => REGISTER ACCESS VIA A READ PORT [patent_app_type] => utility [patent_app_number] => 18/410534 [patent_app_country] => US [patent_app_date] => 2024-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18410534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19303242 [patent_doc_number] => 20240231822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => CONTROL METHOD AND CHIP [patent_app_type] => utility [patent_app_number] => 18/408047 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19129292 [patent_doc_number] => 20240134645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => USING A VECTOR PROCESSOR TO CONFIGURE A DIRECT MEMORY ACCESS SYSTEM FOR FEATURE TRACKING OPERATIONS IN A SYSTEM ON A CHIP [patent_app_type] => utility [patent_app_number] => 18/402519 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 58433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20070653 [patent_doc_number] => 20250208875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => LOAD FUSION [patent_app_type] => utility [patent_app_number] => 18/392187 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18392187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19129297 [patent_doc_number] => 20240134650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => DEVICES TRANSFERRING CACHE LINES, INCLUDING METADATA ON EXTERNAL LINKS [patent_app_type] => utility [patent_app_number] => 18/545603 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545603 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19235913 [patent_doc_number] => 20240193108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE [patent_app_type] => utility [patent_app_number] => 18/545189 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19514183 [patent_doc_number] => 20240345869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SYSTEMS AND METHODS FOR STALLING HOST PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/541670 [patent_app_country] => US [patent_app_date] => 2023-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18541670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19251002 [patent_doc_number] => 20240201992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => ARTIFICIAL INTELLIGENCE PROCESSING APPARATUS, AND DATA PREFETCHING DEVICE AND METHOD FOR ARTIFICIAL INTELLIGENCE PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/539012 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18957489 [patent_doc_number] => 20240045816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => SELF-CONFIGURING BASEBOARD MANAGEMENT CONTROLLER (BMC) [patent_app_type] => utility [patent_app_number] => 18/381614 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18381614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18973893 [patent_doc_number] => 20240053985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => SHARING REGISTER FILE USAGE BETWEEN FUSED PROCESSING RESOURCES [patent_app_type] => utility [patent_app_number] => 18/485089 [patent_app_country] => US [patent_app_date] => 2023-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18485089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19084906 [patent_doc_number] => 20240111707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => MEMORY DEVICES, MODULES AND SYSTEMS HAVING MEMORY DEVICES WITH VARYING PHYSICAL DIMENSIONS, MEMORY FORMATS, AND OPERATIONAL CAPABILITIES [patent_app_type] => utility [patent_app_number] => 18/378000 [patent_app_country] => US [patent_app_date] => 2023-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18925542 [patent_doc_number] => 20240028546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => Network Data Storage Devices having External Access Control [patent_app_type] => utility [patent_app_number] => 18/481047 [patent_app_country] => US [patent_app_date] => 2023-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18481047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18897165 [patent_doc_number] => 20240012650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => METHOD AND PROCESSOR FOR EXECUTING TARGET INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/472457 [patent_app_country] => US [patent_app_date] => 2023-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18472457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19084731 [patent_doc_number] => 20240111532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => LOCK-FREE UNORDERED IN-PLACE COMPACTION [patent_app_type] => utility [patent_app_number] => 18/468642 [patent_app_country] => US [patent_app_date] => 2023-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18468642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19084730 [patent_doc_number] => 20240111531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => FREQUENCY SCALING FOR PER-CORE ACCELERATOR ASSIGNMENTS [patent_app_type] => utility [patent_app_number] => 18/369082 [patent_app_country] => US [patent_app_date] => 2023-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18369082 [rel_patent_id] =>[rel_patent_doc_number] =>)

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