
Hyun Nam
Examiner (ID: 14863, Phone: (571)270-1725 , Office: P/2184 )
| Most Active Art Unit | 2184 |
| Art Unit(s) | 2184, 2183 |
| Total Applications | 1039 |
| Issued Applications | 880 |
| Pending Applications | 63 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10537205
[patent_doc_number] => 09262837
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-16
[patent_title] => 'PCIE clock rate stepping for graphics and platform processors'
[patent_app_type] => utility
[patent_app_number] => 14/607081
[patent_app_country] => US
[patent_app_date] => 2015-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6025
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14607081
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/607081 | PCIE clock rate stepping for graphics and platform processors | Jan 27, 2015 | Issued |
Array
(
[id] => 10249863
[patent_doc_number] => 20150134859
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-14
[patent_title] => 'MULTI-CONFIGURATION COMPUTER'
[patent_app_type] => utility
[patent_app_number] => 14/604193
[patent_app_country] => US
[patent_app_date] => 2015-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 41
[patent_no_of_words] => 9025
[patent_no_of_claims] => 6
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14604193
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/604193 | MULTI-CONFIGURATION COMPUTER | Jan 22, 2015 | |
Array
(
[id] => 10106413
[patent_doc_number] => 09142195
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-22
[patent_title] => 'Data forwarding circuit, data forwarding method, display device, host-side device, and electronic apparatus'
[patent_app_type] => utility
[patent_app_number] => 14/601466
[patent_app_country] => US
[patent_app_date] => 2015-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 23
[patent_no_of_words] => 14951
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 230
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14601466
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/601466 | Data forwarding circuit, data forwarding method, display device, host-side device, and electronic apparatus | Jan 20, 2015 | Issued |
Array
(
[id] => 10235972
[patent_doc_number] => 20150120966
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-30
[patent_title] => 'TECHNIQUES FOR USING AN ASSIGNED SWITCH IDENTIFICATION AT AN INPUT/OUTPUT DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/592774
[patent_app_country] => US
[patent_app_date] => 2015-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 9914
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14592774
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/592774 | Techniques for using an assigned switch identification at an input/output device | Jan 7, 2015 | Issued |
Array
(
[id] => 11131366
[patent_doc_number] => 20160328342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-10
[patent_title] => 'APPARATUS AND METHOD FOR VIRTUALIZING NETWORK INTERFACE'
[patent_app_type] => utility
[patent_app_number] => 15/108229
[patent_app_country] => US
[patent_app_date] => 2014-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3532
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15108229
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/108229 | Apparatus and method for virtualizing network interface | Dec 29, 2014 | Issued |
Array
(
[id] => 10982591
[patent_doc_number] => 20160179535
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-23
[patent_title] => 'METHOD AND APPARATUS FOR EFFICIENT EXECUTION OF NESTED BRANCHES ON A GRAPHICS PROCESSOR UNIT'
[patent_app_type] => utility
[patent_app_number] => 14/581858
[patent_app_country] => US
[patent_app_date] => 2014-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 16140
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581858
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/581858 | Method and apparatus for efficient execution of nested branches on a graphics processor unit | Dec 22, 2014 | Issued |
Array
(
[id] => 11724137
[patent_doc_number] => 09696992
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-04
[patent_title] => 'Apparatus and method for performing a check to optimize instruction flow'
[patent_app_type] => utility
[patent_app_number] => 14/581815
[patent_app_country] => US
[patent_app_date] => 2014-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 22
[patent_no_of_words] => 16388
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581815
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/581815 | Apparatus and method for performing a check to optimize instruction flow | Dec 22, 2014 | Issued |
Array
(
[id] => 12551112
[patent_doc_number] => 10013253
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-03
[patent_title] => Method and apparatus for performing a vector bit reversal
[patent_app_type] => utility
[patent_app_number] => 14/581883
[patent_app_country] => US
[patent_app_date] => 2014-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
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[patent_no_of_words] => 17534
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581883
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/581883 | Method and apparatus for performing a vector bit reversal | Dec 22, 2014 | Issued |
Array
(
[id] => 10982585
[patent_doc_number] => 20160179529
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-23
[patent_title] => 'METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT REVERSAL AND CROSSING'
[patent_app_type] => utility
[patent_app_number] => 14/581738
[patent_app_country] => US
[patent_app_date] => 2014-12-23
[patent_effective_date] => 0000-00-00
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[patent_figures_cnt] => 30
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581738
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/581738 | Method and apparatus for performing a vector bit reversal and crossing | Dec 22, 2014 | Issued |
Array
(
[id] => 11563723
[patent_doc_number] => 09626313
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-18
[patent_title] => 'Trace buffer based replay for context switching'
[patent_app_type] => utility
[patent_app_number] => 14/575498
[patent_app_country] => US
[patent_app_date] => 2014-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 10140
[patent_no_of_claims] => 30
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14575498
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/575498 | Trace buffer based replay for context switching | Dec 17, 2014 | Issued |
Array
(
[id] => 10982603
[patent_doc_number] => 20160179547
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-23
[patent_title] => 'Binary Translation Mechanism'
[patent_app_type] => utility
[patent_app_number] => 14/574797
[patent_app_country] => US
[patent_app_date] => 2014-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14574797
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/574797 | Binary translation mechanism | Dec 17, 2014 | Issued |
Array
(
[id] => 14009679
[patent_doc_number] => 10223299
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-05
[patent_title] => High capacity memory system with improved command-address and chip-select signaling mode
[patent_app_type] => utility
[patent_app_number] => 15/101870
[patent_app_country] => US
[patent_app_date] => 2014-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 60
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15101870
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/101870 | High capacity memory system with improved command-address and chip-select signaling mode | Dec 17, 2014 | Issued |
Array
(
[id] => 11823923
[patent_doc_number] => 20170212859
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-27
[patent_title] => 'MASS STORAGE DEVICE SELECTOR'
[patent_app_type] => utility
[patent_app_number] => 15/101408
[patent_app_country] => US
[patent_app_date] => 2014-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15101408
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/101408 | Mass storage device selector | Dec 7, 2014 | Issued |
Array
(
[id] => 10250241
[patent_doc_number] => 20150135237
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-14
[patent_title] => 'MULTI-PATH VIDEO AND NETWORK CHANNELS'
[patent_app_type] => utility
[patent_app_number] => 14/557282
[patent_app_country] => US
[patent_app_date] => 2014-12-01
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14557282
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/557282 | Multi-path video and network channels | Nov 30, 2014 | Issued |
Array
(
[id] => 11366121
[patent_doc_number] => 20170004102
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-05
[patent_title] => 'REAL-TIME EXECUTION OF MAC CONTROL LOGIC'
[patent_app_type] => utility
[patent_app_number] => 15/100033
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[patent_app_date] => 2014-11-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/100033 | Real-time execution of MAC control logic | Nov 26, 2014 | Issued |
Array
(
[id] => 11124222
[patent_doc_number] => 20160321196
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-03
[patent_title] => 'CIRCUIT FOR CONTROLLING ACCESS TO MEMORY USING ARBITER'
[patent_app_type] => utility
[patent_app_number] => 15/108537
[patent_app_country] => US
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15108537
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/108537 | Circuit for controlling access to memory using arbiter | Nov 26, 2014 | Issued |
Array
(
[id] => 11403812
[patent_doc_number] => 20170024350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-26
[patent_title] => 'ELECTRICAL CONNECTORS'
[patent_app_type] => utility
[patent_app_number] => 15/100219
[patent_app_country] => US
[patent_app_date] => 2014-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15100219
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/100219 | Electrical connectors | Nov 24, 2014 | Issued |
Array
(
[id] => 10801544
[patent_doc_number] => 20160147701
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-26
[patent_title] => 'BRIDGE FOR BUS-POWERED PERIPHERAL DEVICE POWER MANAGEMENT'
[patent_app_type] => utility
[patent_app_number] => 14/549311
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[patent_app_date] => 2014-11-20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/549311 | Bridge for bus-powered peripheral device power management | Nov 19, 2014 | Issued |
Array
(
[id] => 10803566
[patent_doc_number] => 20160149723
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-26
[patent_title] => 'SIGNALING CONTROL AMONG MULTIPLE COMMUNICATION INTERFACES OF AN ELECTRONIC DEVICE BASED ON SIGNAL PRIORITY'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/549138 | Signaling control among multiple communication interfaces of an electronic device based on signal priority | Nov 19, 2014 | Issued |
Array
(
[id] => 10369190
[patent_doc_number] => 20150254195
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-09-10
[patent_title] => 'METHOD AND APPARATUS FOR WIRELESS COMMUNICATION'
[patent_app_type] => utility
[patent_app_number] => 14/547813
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/547813 | METHOD AND APPARATUS FOR WIRELESS COMMUNICATION | Nov 18, 2014 | Abandoned |