Search

Hyun Nam

Examiner (ID: 14863, Phone: (571)270-1725 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184, 2183
Total Applications
1039
Issued Applications
880
Pending Applications
63
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11416736 [patent_doc_number] => 09563563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-07 [patent_title] => 'Multi-stage translation of prefetch requests' [patent_app_type] => utility [patent_app_number] => 14/065700 [patent_app_country] => US [patent_app_date] => 2013-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6682 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14065700 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/065700
Multi-stage translation of prefetch requests Oct 28, 2013 Issued
Array ( [id] => 9437342 [patent_doc_number] => 20140115249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'Parallel Execution Mechanism and Operating Method Thereof' [patent_app_type] => utility [patent_app_number] => 14/061775 [patent_app_country] => US [patent_app_date] => 2013-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2709 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061775 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/061775
Parallel execution mechanism and operating method thereof Oct 23, 2013 Issued
Array ( [id] => 11213691 [patent_doc_number] => 09442727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Filtering out redundant software prefetch instructions' [patent_app_type] => utility [patent_app_number] => 14/053378 [patent_app_country] => US [patent_app_date] => 2013-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14053378 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/053378
Filtering out redundant software prefetch instructions Oct 13, 2013 Issued
Array ( [id] => 9745704 [patent_doc_number] => 20140281422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Method and Apparatus for Sorting Elements in Hardware Structures' [patent_app_type] => utility [patent_app_number] => 14/052571 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8070 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14052571 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/052571
Method and apparatus for sorting elements in hardware structures Oct 10, 2013 Issued
Array ( [id] => 10603148 [patent_doc_number] => 09323714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Processing system with synchronization instruction' [patent_app_type] => utility [patent_app_number] => 14/051140 [patent_app_country] => US [patent_app_date] => 2013-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 10593 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14051140 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/051140
Processing system with synchronization instruction Oct 9, 2013 Issued
Array ( [id] => 9296888 [patent_doc_number] => 20140040522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'UNIVERSAL PERIPHERAL CONNECTOR' [patent_app_type] => utility [patent_app_number] => 14/047617 [patent_app_country] => US [patent_app_date] => 2013-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4807 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14047617 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/047617
Universal peripheral connector Oct 6, 2013 Issued
Array ( [id] => 10210626 [patent_doc_number] => 20150095617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'USING SOFTWARE HAVING CONTROL TRANSFER TERMINATION INSTRUCTIONS WITH SOFTWARE NOT HAVING CONTROL TRANSFER TERMINATION INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/039663 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14039663 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/039663
Using software having control transfer termination instructions with software not having control transfer termination instructions Sep 26, 2013 Issued
Array ( [id] => 9372360 [patent_doc_number] => 20140082233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'PERFORMANCE-ENHANCING HIGH-SPEED INTERFACE CONTROL DEVICE AND DATA TRANSMISSION METHOD' [patent_app_type] => utility [patent_app_number] => 14/030301 [patent_app_country] => US [patent_app_date] => 2013-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2858 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14030301 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/030301
PERFORMANCE-ENHANCING HIGH-SPEED INTERFACE CONTROL DEVICE AND DATA TRANSMISSION METHOD Sep 17, 2013 Abandoned
Array ( [id] => 10841094 [patent_doc_number] => 08868793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'SAS expander system and method for dynamically allocating SAS addresses to SAS expander devices' [patent_app_type] => utility [patent_app_number] => 14/029885 [patent_app_country] => US [patent_app_date] => 2013-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1644 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14029885 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/029885
SAS expander system and method for dynamically allocating SAS addresses to SAS expander devices Sep 17, 2013 Issued
Array ( [id] => 9224862 [patent_doc_number] => 20140019637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'METHOD, SYSTEM AND APPARATUS FOR MANAGEMENT OF PUSH CONTENT' [patent_app_type] => utility [patent_app_number] => 14/028582 [patent_app_country] => US [patent_app_date] => 2013-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5755 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14028582 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/028582
Method, system and apparatus for management of push content Sep 16, 2013 Issued
Array ( [id] => 11860747 [patent_doc_number] => 09740430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Optimizing parallel build of application' [patent_app_type] => utility [patent_app_number] => 14/028753 [patent_app_country] => US [patent_app_date] => 2013-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14028753 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/028753
Optimizing parallel build of application Sep 16, 2013 Issued
Array ( [id] => 10576011 [patent_doc_number] => 09298657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Semiconductor device and data processing system' [patent_app_type] => utility [patent_app_number] => 14/011336 [patent_app_country] => US [patent_app_date] => 2013-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 12541 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14011336 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/011336
Semiconductor device and data processing system Aug 26, 2013 Issued
Array ( [id] => 12475215 [patent_doc_number] => 09990323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Configuring a communication interconnect for electronic devices [patent_app_type] => utility [patent_app_number] => 14/902513 [patent_app_country] => US [patent_app_date] => 2013-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4044 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14902513 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/902513
Configuring a communication interconnect for electronic devices Jul 30, 2013 Issued
Array ( [id] => 10793915 [patent_doc_number] => 20160140072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'TWO-DIMENSIONAL TORUS TOPOLOGY' [patent_app_type] => utility [patent_app_number] => 14/903256 [patent_app_country] => US [patent_app_date] => 2013-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4046 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14903256 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/903256
Two-dimensional torus topology Jul 29, 2013 Issued
Array ( [id] => 9305462 [patent_doc_number] => 20140044136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'HART ANALOG INPUT MODULE WITH DIFFERENTIAL INPUT STAGE' [patent_app_type] => utility [patent_app_number] => 13/953537 [patent_app_country] => US [patent_app_date] => 2013-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4436 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13953537 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/953537
HART analog input module with differential input stage Jul 28, 2013 Issued
Array ( [id] => 11037082 [patent_doc_number] => 20160234038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'A TRANSCEIVER CIRCUIT AND METHOD FOR CONTROLLER AREA NETWORKS' [patent_app_type] => utility [patent_app_number] => 14/899587 [patent_app_country] => US [patent_app_date] => 2013-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7476 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14899587 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/899587
Transceiver circuit and method for controller area networks Jul 23, 2013 Issued
Array ( [id] => 9150706 [patent_doc_number] => 20130305229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'ANALYSIS OF DYNAMIC ELEMENTS IN BOUNDED TIME' [patent_app_type] => utility [patent_app_number] => 13/945783 [patent_app_country] => US [patent_app_date] => 2013-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13945783 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/945783
Analysis of dynamic elements in bounded time Jul 17, 2013 Issued
Array ( [id] => 10320746 [patent_doc_number] => 20150205751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'Reducing Unwanted Reflections in Source-Terminated Channels' [patent_app_type] => utility [patent_app_number] => 14/411723 [patent_app_country] => US [patent_app_date] => 2013-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3727 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14411723 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/411723
Reducing unwanted reflections in source-terminated channels Jul 16, 2013 Issued
Array ( [id] => 9213834 [patent_doc_number] => 20140013011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'DEBUG ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/938046 [patent_app_country] => US [patent_app_date] => 2013-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15524 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13938046 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/938046
Prioritising event data over configuration data in a single interface in a SoC/debug architecture Jul 8, 2013 Issued
Array ( [id] => 9224952 [patent_doc_number] => 20140019727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'MODIFIED BALANCED THROUGHPUT DATA-PATH ARCHITECTURE FOR SPECIAL CORRELATION APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 13/936886 [patent_app_country] => US [patent_app_date] => 2013-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3942 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13936886 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/936886
Modified balanced throughput data-path architecture for special correlation applications Jul 7, 2013 Issued
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