Hyun Nam

Array ( [id] => 19828021 [patent_doc_number] => 12248805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Focus controlling method, electronic device and storage medium [patent_app_type] => utility [patent_app_number] => 17/681068 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 9148 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17681068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19313043 [patent_doc_number] => 12038855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Memory system with adaptive refresh [patent_app_type] => utility [patent_app_number] => 17/650455 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 8086 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18316709 [patent_doc_number] => 11630790 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-04-18 [patent_title] => Integrated circuit and interrupt-handling method of sensing device [patent_app_type] => utility [patent_app_number] => 17/666978 [patent_app_country] => US [patent_app_date] => 2022-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6086 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17666978 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18965832 [patent_doc_number] => 11899597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => High capacity memory system with improved command-address and chip-select signaling mode [patent_app_type] => utility [patent_app_number] => 17/649773 [patent_app_country] => US [patent_app_date] => 2022-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 76 [patent_no_of_words] => 31845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17649773 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19243734 [patent_doc_number] => 12014179 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-06-18 [patent_title] => Function interposition in an observability pipeline system [patent_app_type] => utility [patent_app_number] => 17/589002 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13531 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18539517 [patent_doc_number] => 20230244625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => LOGICAL MESSAGE INTERFACE FOR CONFIGURING AND MANAGING A PHYSICAL DEVICE IN SINGLE AND MULTI-HOST SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/588675 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19762829 [patent_doc_number] => 12221101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Automated cruise control system [patent_app_type] => utility [patent_app_number] => 17/588096 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 81 [patent_no_of_words] => 65899 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18531893 [patent_doc_number] => 20230236965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => ENHANCEMENTS TO DATAGEN ALGORITHM TO GAIN ADDITIONAL PERFORMANCE FOR L1 DATASET [patent_app_type] => utility [patent_app_number] => 17/649134 [patent_app_country] => US [patent_app_date] => 2022-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17649134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18592001 [patent_doc_number] => 11740899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => In-memory associative processing system [patent_app_type] => utility [patent_app_number] => 17/577977 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 18725 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17706789 [patent_doc_number] => 20220206795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => SHARING REGISTER FILE USAGE BETWEEN FUSED PROCESSING RESOURCES [patent_app_type] => utility [patent_app_number] => 17/569229 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19375390 [patent_doc_number] => 12066955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => System and method for enhancing throughput during data transfer [patent_app_type] => utility [patent_app_number] => 17/565779 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18527783 [patent_doc_number] => 11714776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Enabling a multi-chip daisy chain topology using peripheral component interconnect express (PCIe) [patent_app_type] => utility [patent_app_number] => 17/564975 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17550262 [patent_doc_number] => 20220121604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => NETWORK-ON-CHIP DATA PROCESSING METHOD AND DEVICE [patent_app_type] => utility [patent_app_number] => 17/564579 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17613935 [patent_doc_number] => 20220156215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => NETWORK-ON-CHIP DATA PROCESSING METHOD AND DEVICE [patent_app_type] => utility [patent_app_number] => 17/564366 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18454190 [patent_doc_number] => 20230195470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => BEHAVIORAL IMPLEMENTATION OF A DOUBLE FAULT STACK IN A COMPUTER SYSTEM [patent_app_type] => utility [patent_app_number] => 17/559346 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20281962 [patent_doc_number] => 20250307204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => A NETWORK ON CHIP PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/259235 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18259235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19493482 [patent_doc_number] => 12112199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Interruptible LZO decompression [patent_app_type] => utility [patent_app_number] => 17/456937 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4288 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18316587 [patent_doc_number] => 11630668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-04-18 [patent_title] => Processor with smart cache in place of register file for providing operands [patent_app_type] => utility [patent_app_number] => 17/529804 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17462436 [patent_doc_number] => 20220075741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => MEMORY SUB-SYSTEM MANUFACTURING MODE [patent_app_type] => utility [patent_app_number] => 17/524814 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17613848 [patent_doc_number] => 20220156128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => COMPUTING DEVICE, COMPUTING EQUIPMENT AND PROGRAMMABLE SCHEDULING METHOD [patent_app_type] => utility [patent_app_number] => 17/524700 [patent_app_country] => US [patent_app_date] => 2021-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524700 [rel_patent_id] =>[rel_patent_doc_number] =>)