Search

Ian F. Whitmore

Examiner (ID: 621, Phone: (571)270-3842 , Office: P/2923 )

Most Active Art Unit
2923
Art Unit(s)
2953, 2923
Total Applications
1307
Issued Applications
1276
Pending Applications
7
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20580225 [patent_doc_number] => 12572476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => GPU chiplets using high bandwidth crosslinks [patent_app_type] => utility [patent_app_number] => 19/337250 [patent_app_country] => US [patent_app_date] => 2025-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19337250 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/337250
GPU chiplets using high bandwidth crosslinks Sep 22, 2025 Issued
Array ( [id] => 20601636 [patent_doc_number] => 20260079645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 19/060872 [patent_app_country] => US [patent_app_date] => 2025-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19060872 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/060872
MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY Feb 23, 2025 Pending
Array ( [id] => 20249866 [patent_doc_number] => 20250298735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => INTERLEAVED MEMORY TRANSACTION TRACKING FOR TRANSACTIONS WITH UNRELATED LENGTHS [patent_app_type] => utility [patent_app_number] => 19/059031 [patent_app_country] => US [patent_app_date] => 2025-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19059031 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/059031
INTERLEAVED MEMORY TRANSACTION TRACKING FOR TRANSACTIONS WITH UNRELATED LENGTHS Feb 19, 2025 Pending
Array ( [id] => 20043056 [patent_doc_number] => 20250181278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => IMPLEMENTING COHERENCY AND PAGE CACHE SUPPORT IN A DISTRIBUTED WAY FOR FILES [patent_app_type] => utility [patent_app_number] => 19/045014 [patent_app_country] => US [patent_app_date] => 2025-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19045014 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/045014
IMPLEMENTING COHERENCY AND PAGE CACHE SUPPORT IN A DISTRIBUTED WAY FOR FILES Feb 3, 2025 Pending
Array ( [id] => 20137831 [patent_doc_number] => 20250244875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => APPARATUS AND METHOD WITH CHECKPOINT DATA PROCESSING [patent_app_type] => utility [patent_app_number] => 19/018818 [patent_app_country] => US [patent_app_date] => 2025-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19018818 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/018818
APPARATUS AND METHOD WITH CHECKPOINT DATA PROCESSING Jan 12, 2025 Pending
Array ( [id] => 20087121 [patent_doc_number] => 20250217057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => MANAGEMENT OF OPERATING SYSTEM SOFTWARE USING READ-ONLY MULTI-ATTACH BLOCK VOLUMES [patent_app_type] => utility [patent_app_number] => 19/008450 [patent_app_country] => US [patent_app_date] => 2025-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19008450 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/008450
MANAGEMENT OF OPERATING SYSTEM SOFTWARE USING READ-ONLY MULTI-ATTACH BLOCK VOLUMES Jan 1, 2025 Pending
Array ( [id] => 19899138 [patent_doc_number] => 12277059 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-04-15 [patent_title] => Method and apparatus for reducing mirror data transmission amount by dual layer cache, and device and medium [patent_app_type] => utility [patent_app_number] => 18/989585 [patent_app_country] => US [patent_app_date] => 2024-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 3664 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18989585 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/989585
Method and apparatus for reducing mirror data transmission amount by dual layer cache, and device and medium Dec 19, 2024 Issued
Array ( [id] => 20123117 [patent_doc_number] => 20250238148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => AUTHENTICATION SERVER, AUTHENTICATION SYSTEM, AND AUTHENTICATION METHOD [patent_app_type] => utility [patent_app_number] => 18/974050 [patent_app_country] => US [patent_app_date] => 2024-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18974050 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/974050
AUTHENTICATION SERVER, AUTHENTICATION SYSTEM, AND AUTHENTICATION METHOD Dec 8, 2024 Pending
Array ( [id] => 20234421 [patent_doc_number] => 20250291740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => PROCESSOR AND METHOD FOR MEMORY ACCESS INSTRUCTION, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/965888 [patent_app_country] => US [patent_app_date] => 2024-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18965888 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/965888
PROCESSOR AND METHOD FOR MEMORY ACCESS INSTRUCTION, AND ELECTRONIC DEVICE Dec 1, 2024 Pending
Array ( [id] => 19756638 [patent_doc_number] => 20250045203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => SELECTIVELY-ACTIVATED TERMINATION CIRCUITRY, AND ASSOCIATED SYSTEMS, METHODS, AND DEVICES [patent_app_type] => utility [patent_app_number] => 18/926690 [patent_app_country] => US [patent_app_date] => 2024-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18926690 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/926690
SELECTIVELY-ACTIVATED TERMINATION CIRCUITRY, AND ASSOCIATED SYSTEMS, METHODS, AND DEVICES Oct 24, 2024 Pending
Array ( [id] => 19756409 [patent_doc_number] => 20250044974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => GARBAGE COLLECTION FOR OBJECT-BASED STORAGE SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/920644 [patent_app_country] => US [patent_app_date] => 2024-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18920644 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/920644
Garbage collection for object-based storage systems Oct 17, 2024 Issued
Array ( [id] => 20494087 [patent_doc_number] => 12535956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Semiconductor memory device and memory system including the same [patent_app_type] => utility [patent_app_number] => 18/907760 [patent_app_country] => US [patent_app_date] => 2024-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 14380 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18907760 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/907760
Semiconductor memory device and memory system including the same Oct 6, 2024 Issued
Array ( [id] => 20000783 [patent_doc_number] => 20250139005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => CACHE-DESIGNING METHOD WHERE CACHE DATA AND CACHE-MISS INFORMATION SHARE THE SAME STORAGE SPACE [patent_app_type] => utility [patent_app_number] => 18/893397 [patent_app_country] => US [patent_app_date] => 2024-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18893397 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/893397
Cache-designing method where cache data and cache-miss information share the same storage space Sep 22, 2024 Issued
Array ( [id] => 19834325 [patent_doc_number] => 20250086111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => PRE-OPTIMIZER AND OPTIMIZER BASED FRAMEWORK FOR OPTIMAL DEPLOYMENT OF EMBEDDING TABLES ACROSS HETEROGENEOUS MEMORY ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/804270 [patent_app_country] => US [patent_app_date] => 2024-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 647 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18804270 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/804270
Pre-optimizer and optimizer based framework for optimal deployment of embedding tables across heterogeneous memory architecture Aug 13, 2024 Issued
Array ( [id] => 19633006 [patent_doc_number] => 20240411455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => METHODS TO CONFIGURE AND ACCESS SCALABLE OBJECT STORES USING KV-SSDS AND HYBRID BACKEND STORAGE TIERS OF KV-SSDS, NVME-SSDS AND OTHER FLASH DEVICES [patent_app_type] => utility [patent_app_number] => 18/805524 [patent_app_country] => US [patent_app_date] => 2024-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18805524 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/805524
METHODS TO CONFIGURE AND ACCESS SCALABLE OBJECT STORES USING KV-SSDS AND HYBRID BACKEND STORAGE TIERS OF KV-SSDS, NVME-SSDS AND OTHER FLASH DEVICES Aug 13, 2024 Pending
Array ( [id] => 20595162 [patent_doc_number] => 12578878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Storage system processing without global locks [patent_app_type] => utility [patent_app_number] => 18/781801 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781801 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781801
Storage system processing without global locks Jul 22, 2024 Issued
Array ( [id] => 20273753 [patent_doc_number] => 12443535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Joint scheduler for high bandwidth multi-shot prefetching [patent_app_type] => utility [patent_app_number] => 18/770690 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5826 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770690 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770690
Joint scheduler for high bandwidth multi-shot prefetching Jul 11, 2024 Issued
Array ( [id] => 19695023 [patent_doc_number] => 20250013568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => Data Pattern Based Cache Management [patent_app_type] => utility [patent_app_number] => 18/769994 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769994
Data Pattern Based Cache Management Jul 10, 2024 Pending
Array ( [id] => 19546137 [patent_doc_number] => 20240363173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => MODULATION OF SOURCE VOLTAGE IN NAND-FLASH ARRAY READ [patent_app_type] => utility [patent_app_number] => 18/768091 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768091
MODULATION OF SOURCE VOLTAGE IN NAND-FLASH ARRAY READ Jul 9, 2024 Pending
Array ( [id] => 19878616 [patent_doc_number] => 20250110873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => SYSTEMS, METHODS, AND APPARATUS FOR CACHE MANAGEMENT IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/749563 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749563 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749563
SYSTEMS, METHODS, AND APPARATUS FOR CACHE MANAGEMENT IN A MEMORY DEVICE Jun 19, 2024 Pending
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