Search

Ian F. Whitmore

Examiner (ID: 621, Phone: (571)270-3842 , Office: P/2923 )

Most Active Art Unit
2923
Art Unit(s)
2953, 2923
Total Applications
1307
Issued Applications
1276
Pending Applications
7
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20228530 [patent_doc_number] => 12417182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => De-prioritizing speculative code lines in on-chip caches [patent_app_type] => utility [patent_app_number] => 17/551172 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3413 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551172 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/551172
De-prioritizing speculative code lines in on-chip caches Dec 13, 2021 Issued
Array ( [id] => 17507296 [patent_doc_number] => 20220100399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => TRANSACTION PROCESSING WITH DIFFERING CAPACITY STORAGE [patent_app_type] => utility [patent_app_number] => 17/548112 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548112 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548112
Transaction processing with differing capacity storage Dec 9, 2021 Issued
Array ( [id] => 18638081 [patent_doc_number] => 11762683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Merging data for write allocate [patent_app_type] => utility [patent_app_number] => 17/542573 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 17673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542573 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542573
Merging data for write allocate Dec 5, 2021 Issued
Array ( [id] => 18414907 [patent_doc_number] => 11669449 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-06 [patent_title] => Ghost list cache eviction [patent_app_type] => utility [patent_app_number] => 17/457000 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457000 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457000
Ghost list cache eviction Nov 29, 2021 Issued
Array ( [id] => 17430248 [patent_doc_number] => 20220057957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => METHOD AND APPARATUS FOR CONTROLLING DIFFERENT TYPES OF STORAGE UNITS [patent_app_type] => utility [patent_app_number] => 17/519685 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519685 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/519685
Method and apparatus for controlling different types of storage units Nov 4, 2021 Issued
Array ( [id] => 17430230 [patent_doc_number] => 20220057939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => TECHNIQUES TO UPDATE A TRIM PARAMETER IN NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/518154 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518154 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518154
Techniques to update a trim parameter in non-volatile memory Nov 2, 2021 Issued
Array ( [id] => 18234903 [patent_doc_number] => 11599462 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-07 [patent_title] => Memory cache entry management with pinned cache entries [patent_app_type] => utility [patent_app_number] => 17/518467 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 11474 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518467 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518467
Memory cache entry management with pinned cache entries Nov 2, 2021 Issued
Array ( [id] => 18087381 [patent_doc_number] => 11537517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Memory device for supporting cache read operation, operating method thereof, and memory system including the same [patent_app_type] => utility [patent_app_number] => 17/492851 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492851 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/492851
Memory device for supporting cache read operation, operating method thereof, and memory system including the same Oct 3, 2021 Issued
Array ( [id] => 18087380 [patent_doc_number] => 11537516 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-27 [patent_title] => Multi-tier cache for a distributed storage system [patent_app_type] => utility [patent_app_number] => 17/491004 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 26980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491004 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491004
Multi-tier cache for a distributed storage system Sep 29, 2021 Issued
Array ( [id] => 18279989 [patent_doc_number] => 20230095461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => Using Epoch Counter Values for Controlling the Retention of Cache Blocks in a Cache [patent_app_type] => utility [patent_app_number] => 17/491478 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491478 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491478
Using epoch counter values for controlling the retention of cache blocks in a cache Sep 29, 2021 Issued
Array ( [id] => 18316691 [patent_doc_number] => 11630772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-04-18 [patent_title] => Suppressing cache line modification [patent_app_type] => utility [patent_app_number] => 17/489702 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17489702 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/489702
Suppressing cache line modification Sep 28, 2021 Issued
Array ( [id] => 17977443 [patent_doc_number] => 11494303 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-08 [patent_title] => Data storage system with adaptive, memory-efficient cache flushing structure [patent_app_type] => utility [patent_app_number] => 17/488644 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 9959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488644 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488644
Data storage system with adaptive, memory-efficient cache flushing structure Sep 28, 2021 Issued
Array ( [id] => 17484481 [patent_doc_number] => 20220091985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => ELECTRONIC APPARATUS AND INFORMATION PROVIDING METHOD USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/448504 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448504 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448504
Electronic apparatus and information providing method using the same Sep 21, 2021 Issued
Array ( [id] => 18269731 [patent_doc_number] => 20230090973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => IMMEDIATE OFFSET OF LOAD STORE AND ATOMIC INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/480528 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 49555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480528 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480528
Immediate offset of load store and atomic instructions Sep 20, 2021 Issued
Array ( [id] => 17992172 [patent_doc_number] => 20220358209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Thwarting Store-to-Load Forwarding Side Channel Attacks by Pre-Forwarding Matching of Physical Address Proxies and/or Permission Checking [patent_app_type] => utility [patent_app_number] => 17/472376 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472376 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472376
Thwarting store-to-load forwarding side channel attacks by pre-forwarding matching of physical address proxies and/or permission checking Sep 9, 2021 Issued
Array ( [id] => 17294212 [patent_doc_number] => 20210390051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => HARDWARE COHERENCE FOR MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 17/460439 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460439
Hardware coherence for memory controller Aug 29, 2021 Issued
Array ( [id] => 18387083 [patent_doc_number] => 11657872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Disturb management based on write times [patent_app_type] => utility [patent_app_number] => 17/460415 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6986 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460415 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460415
Disturb management based on write times Aug 29, 2021 Issued
Array ( [id] => 17446427 [patent_doc_number] => 20220066932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => METHOD AND SYSTEM FOR PREDICTIVELY CACHING DATA [patent_app_type] => utility [patent_app_number] => 17/446051 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446051 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446051
Method and system for predictively caching data Aug 25, 2021 Issued
Array ( [id] => 18606796 [patent_doc_number] => 11748262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Predictive data storage hierarchical memory systems and methods [patent_app_type] => utility [patent_app_number] => 17/411719 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 24989 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411719 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411719
Predictive data storage hierarchical memory systems and methods Aug 24, 2021 Issued
Array ( [id] => 18386205 [patent_doc_number] => 11656986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Distributed generic cacheability analysis [patent_app_type] => utility [patent_app_number] => 17/407594 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6611 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407594 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407594
Distributed generic cacheability analysis Aug 19, 2021 Issued
Menu