Search

Ian F. Whitmore

Examiner (ID: 621, Phone: (571)270-3842 , Office: P/2923 )

Most Active Art Unit
2923
Art Unit(s)
2953, 2923
Total Applications
1307
Issued Applications
1276
Pending Applications
7
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19617534 [patent_doc_number] => 20240403214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => Routing Circuit for Computer Resource Topology [patent_app_type] => utility [patent_app_number] => 18/747917 [patent_app_country] => US [patent_app_date] => 2024-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747917 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/747917
Routing circuit for computer resource topology Jun 18, 2024 Issued
Array ( [id] => 19794816 [patent_doc_number] => 12235763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Data processing method, device, computer apparatus and storage medium [patent_app_type] => utility [patent_app_number] => 18/741900 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 10507 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741900 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741900
Data processing method, device, computer apparatus and storage medium Jun 12, 2024 Issued
Array ( [id] => 19794816 [patent_doc_number] => 12235763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Data processing method, device, computer apparatus and storage medium [patent_app_type] => utility [patent_app_number] => 18/741900 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 10507 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741900 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741900
Data processing method, device, computer apparatus and storage medium Jun 12, 2024 Issued
Array ( [id] => 19794816 [patent_doc_number] => 12235763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Data processing method, device, computer apparatus and storage medium [patent_app_type] => utility [patent_app_number] => 18/741900 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 10507 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741900 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741900
Data processing method, device, computer apparatus and storage medium Jun 12, 2024 Issued
Array ( [id] => 19794816 [patent_doc_number] => 12235763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Data processing method, device, computer apparatus and storage medium [patent_app_type] => utility [patent_app_number] => 18/741900 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 10507 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741900 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741900
Data processing method, device, computer apparatus and storage medium Jun 12, 2024 Issued
Array ( [id] => 20481818 [patent_doc_number] => 12530293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => System and method for processing queries against semantic cache entries using unique distance-based thresholds [patent_app_type] => utility [patent_app_number] => 18/737366 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18737366 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/737366
System and method for processing queries against semantic cache entries using unique distance-based thresholds Jun 6, 2024 Issued
Array ( [id] => 20181232 [patent_doc_number] => 20250265190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => SYSTEMS AND METHODS OF CACHE DATA PLACEMENT [patent_app_type] => utility [patent_app_number] => 18/677868 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677868 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677868
SYSTEMS AND METHODS OF CACHE DATA PLACEMENT May 28, 2024 Pending
Array ( [id] => 19420006 [patent_doc_number] => 20240296129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => VICTIM CACHE WITH WRITE MISS MERGING [patent_app_type] => utility [patent_app_number] => 18/659407 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659407 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/659407
Victim cache with write miss merging May 8, 2024 Issued
Array ( [id] => 19856954 [patent_doc_number] => 12259788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Configurable entity-based undo and redo operations [patent_app_type] => utility [patent_app_number] => 18/653558 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7761 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653558 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653558
Configurable entity-based undo and redo operations May 1, 2024 Issued
Array ( [id] => 19362918 [patent_doc_number] => 20240264952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES [patent_app_type] => utility [patent_app_number] => 18/639013 [patent_app_country] => US [patent_app_date] => 2024-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18639013 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/639013
Victim cache that supports draining write-miss entries Apr 17, 2024 Issued
Array ( [id] => 19369467 [patent_doc_number] => 12061549 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-08-13 [patent_title] => Multiprocessor system and data management method thereof [patent_app_type] => utility [patent_app_number] => 18/637136 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7919 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637136 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637136
Multiprocessor system and data management method thereof Apr 15, 2024 Issued
Array ( [id] => 20296650 [patent_doc_number] => 20250321893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => TILE LEVEL INTERCONNECT DESIGN FOR CENTRAL PROCESSING UNIT IMAGE ACCESS PATTERNS [patent_app_type] => utility [patent_app_number] => 18/633279 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633279 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/633279
Tile level interconnect design for central processing unit image access patterns Apr 10, 2024 Issued
Array ( [id] => 20550462 [patent_doc_number] => 12561255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Prefetch kill and revival in an instruction cache [patent_app_type] => utility [patent_app_number] => 18/630098 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630098 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/630098
Prefetch kill and revival in an instruction cache Apr 8, 2024 Issued
Array ( [id] => 19320283 [patent_doc_number] => 20240241827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => SUPPRESSING CACHE LINE MODIFICATION [patent_app_type] => utility [patent_app_number] => 18/621799 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621799 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/621799
Suppressing cache line modification Mar 28, 2024 Issued
Array ( [id] => 20281915 [patent_doc_number] => 20250307157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => Prefetch Throttling based on Cache Thrashing [patent_app_type] => utility [patent_app_number] => 18/619818 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18619818 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/619818
Prefetch Throttling based on Cache Thrashing Mar 27, 2024 Pending
Array ( [id] => 19482141 [patent_doc_number] => 20240330183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => MULTI-CHIPLET MODULE SYSTEM, METHOD AND DEVICE [patent_app_type] => utility [patent_app_number] => 18/607491 [patent_app_country] => US [patent_app_date] => 2024-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7331 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607491 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607491
Multi-chiplet module system, method and device Mar 16, 2024 Issued
Array ( [id] => 19827928 [patent_doc_number] => 12248710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Implementing coherency and page cache support in a distributed way for files [patent_app_type] => utility [patent_app_number] => 18/599881 [patent_app_country] => US [patent_app_date] => 2024-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9051 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18599881 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/599881
Implementing coherency and page cache support in a distributed way for files Mar 7, 2024 Issued
Array ( [id] => 19911520 [patent_doc_number] => 12287729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Neural processing device and method for transmitting data thereof [patent_app_type] => utility [patent_app_number] => 18/599031 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 17717 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18599031 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/599031
Neural processing device and method for transmitting data thereof Mar 6, 2024 Issued
Array ( [id] => 20009661 [patent_doc_number] => 20250147883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => COMPUTER SYSTEM AND METHOD EXECUTED BY COMPUTER SYSTEM [patent_app_type] => utility [patent_app_number] => 18/592777 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18592777 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/592777
Computer system and method executed by computer system Feb 29, 2024 Issued
Array ( [id] => 20110179 [patent_doc_number] => 12360900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Processor, system, and method for dynamic cache allocation [patent_app_type] => utility [patent_app_number] => 18/589852 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18589852 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/589852
Processor, system, and method for dynamic cache allocation Feb 27, 2024 Issued
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