Search

Ian F. Whitmore

Examiner (ID: 621, Phone: (571)270-3842 , Office: P/2923 )

Most Active Art Unit
2923
Art Unit(s)
2953, 2923
Total Applications
1307
Issued Applications
1276
Pending Applications
7
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19544919 [patent_doc_number] => 20240361955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => MEMORY CONTROLLER AND MEMORY SYSTEM PERFORMING WEAR-LEVELING [patent_app_type] => utility [patent_app_number] => 18/199246 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18199246 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/199246
Memory controller and memory system performing wear-leveling May 17, 2023 Issued
Array ( [id] => 20388207 [patent_doc_number] => 12487933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Cache grouping for increasing performance and fairness in shared caches [patent_app_type] => utility [patent_app_number] => 18/319016 [patent_app_country] => US [patent_app_date] => 2023-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18319016 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/319016
Cache grouping for increasing performance and fairness in shared caches May 16, 2023 Issued
Array ( [id] => 18925217 [patent_doc_number] => 20240028221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/302276 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302276 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/302276
Semiconductor memory device and memory system including the same Apr 17, 2023 Issued
Array ( [id] => 19078090 [patent_doc_number] => 11947455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Suppressing cache line modification [patent_app_type] => utility [patent_app_number] => 18/135555 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5212 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18135555 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/135555
Suppressing cache line modification Apr 16, 2023 Issued
Array ( [id] => 19340344 [patent_doc_number] => 12050532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Routing circuit for computer resource topology [patent_app_type] => utility [patent_app_number] => 18/296861 [patent_app_country] => US [patent_app_date] => 2023-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 26 [patent_no_of_words] => 15778 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18296861 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/296861
Routing circuit for computer resource topology Apr 5, 2023 Issued
Array ( [id] => 19152580 [patent_doc_number] => 11977491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Prefetch kill and revival in an instruction cache [patent_app_type] => utility [patent_app_number] => 18/194708 [patent_app_country] => US [patent_app_date] => 2023-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194708 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/194708
Prefetch kill and revival in an instruction cache Apr 2, 2023 Issued
Array ( [id] => 19885872 [patent_doc_number] => 12271588 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-04-08 [patent_title] => Prioritization of memory traffic for multi-process workloads [patent_app_type] => utility [patent_app_number] => 18/192971 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18192971 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/192971
Prioritization of memory traffic for multi-process workloads Mar 29, 2023 Issued
Array ( [id] => 19369707 [patent_doc_number] => 12061792 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-08-13 [patent_title] => Method of handling host write commands requesting to write dummy pattern on flash memory and related memory controller and storage system [patent_app_type] => utility [patent_app_number] => 18/122134 [patent_app_country] => US [patent_app_date] => 2023-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4503 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18122134 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/122134
Method of handling host write commands requesting to write dummy pattern on flash memory and related memory controller and storage system Mar 15, 2023 Issued
Array ( [id] => 18422292 [patent_doc_number] => 20230176756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, INFORMATION PROCESSING PROGRAM, AND MAGNETIC TAPE CARTRIDGE [patent_app_type] => utility [patent_app_number] => 18/165284 [patent_app_country] => US [patent_app_date] => 2023-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18165284 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/165284
INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, INFORMATION PROCESSING PROGRAM, AND MAGNETIC TAPE CARTRIDGE Feb 5, 2023 Abandoned
Array ( [id] => 19375682 [patent_doc_number] => 12067252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Storage device writing data on the basis of temperatures of memory dies and method thereof [patent_app_type] => utility [patent_app_number] => 18/163073 [patent_app_country] => US [patent_app_date] => 2023-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8317 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18163073 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/163073
Storage device writing data on the basis of temperatures of memory dies and method thereof Jan 31, 2023 Issued
Array ( [id] => 18694704 [patent_doc_number] => 20230325120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => TECHNIQUES FOR FOUR CYCLE ACCESS COMMANDS [patent_app_type] => utility [patent_app_number] => 18/161757 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18161757 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/161757
Techniques for four cycle access commands Jan 29, 2023 Issued
Array ( [id] => 18359548 [patent_doc_number] => 20230141139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => WRITE CACHE CIRCUIT, DATA WRITE METHOD, AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/149247 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149247 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149247
Write cache circuit, data write method, and memory Jan 2, 2023 Issued
Array ( [id] => 20550269 [patent_doc_number] => 12561060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Partial address memory requests [patent_app_type] => utility [patent_app_number] => 18/147088 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18147088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/147088
Partial address memory requests Dec 27, 2022 Issued
Array ( [id] => 19794815 [patent_doc_number] => 12235762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-02-25 [patent_title] => Data access method and apparatus, device, and non-transitory readable storage medium [patent_app_type] => utility [patent_app_number] => 18/724508 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 15935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18724508 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/724508
Data access method and apparatus, device, and non-transitory readable storage medium Dec 26, 2022 Issued
Array ( [id] => 19250885 [patent_doc_number] => 20240201875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => MANAGING DATA RELIABILITY IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/082932 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18082932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/082932
Managing data reliability in semiconductor devices Dec 15, 2022 Issued
Array ( [id] => 19235883 [patent_doc_number] => 20240193078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => TECHNIQUES TO ALLOCATE MEMORY FOR IN-LINE OR IN-BAND ERROR CORRECTION CONTROL [patent_app_type] => utility [patent_app_number] => 18/078984 [patent_app_country] => US [patent_app_date] => 2022-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10522 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18078984 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/078984
TECHNIQUES TO ALLOCATE MEMORY FOR IN-LINE OR IN-BAND ERROR CORRECTION CONTROL Dec 10, 2022 Pending
Array ( [id] => 18377903 [patent_doc_number] => 20230152990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => SYSTEM ON CHIP AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/987551 [patent_app_country] => US [patent_app_date] => 2022-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17987551 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/987551
System on chip and operation method thereof Nov 14, 2022 Issued
Array ( [id] => 18238992 [patent_doc_number] => 20230071303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => METHODS AND SYSTEMS FOR MAINTAINING CACHE COHERENCY BETWEEN NODES IN A CLUSTERED ENVIRONMENT BY PERFORMING A BITMAP LOOKUP IN RESPONSE TO A READ REQUEST FROM ONE OF THE NODES [patent_app_type] => utility [patent_app_number] => 18/055174 [patent_app_country] => US [patent_app_date] => 2022-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18055174 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/055174
Methods and systems for maintaining cache coherency between nodes in a clustered environment by performing a bitmap lookup in response to a read request from one of the nodes Nov 13, 2022 Issued
Array ( [id] => 18228300 [patent_doc_number] => 20230067294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => PEAK POWER MANAGEMENT IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/983177 [patent_app_country] => US [patent_app_date] => 2022-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17983177 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/983177
Peak power management in a memory device Nov 7, 2022 Issued
Array ( [id] => 19144586 [patent_doc_number] => 20240143503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => VARIED VALIDITY BIT PLACEMENT IN TAG BITS OF A MEMORY [patent_app_type] => utility [patent_app_number] => 17/974888 [patent_app_country] => US [patent_app_date] => 2022-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17974888 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/974888
Varied validity bit placement in tag bits of a memory Oct 26, 2022 Issued
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