Ian F. Whitmore

Array ( [id] => 18196743 [patent_doc_number] => 20230050262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => HOST, OPERATING METHOD OF HOST AND STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 17/817714 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17817714 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19078106 [patent_doc_number] => 11947471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Unsuccessful write retry buffer [patent_app_type] => utility [patent_app_number] => 17/852135 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6449 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19794813 [patent_doc_number] => 12235760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Apparatus having selectively-activated termination circuitry [patent_app_type] => utility [patent_app_number] => 17/851273 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6736 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17931936 [patent_doc_number] => 20220327061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => PACKET PROCESSING DEVICE TO DETERMINE MEMORY TO STORE DATA IN A SERVER ARCHITECTURE AND COMPUTING SYSTEM INCLUDING SAME [patent_app_type] => utility [patent_app_number] => 17/847851 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17847851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18846839 [patent_doc_number] => 20230409243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => LOGICAL MEMORY ADDRESSING FOR NETWORK DEVICES [patent_app_type] => utility [patent_app_number] => 17/845740 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18912066 [patent_doc_number] => 11875045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Semiconductor memory and method for density configuring of bank of semiconductor memory [patent_app_type] => utility [patent_app_number] => 17/844205 [patent_app_country] => US [patent_app_date] => 2022-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11450 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17844205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17869286 [patent_doc_number] => 20220292023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => VICTIM CACHE WITH WRITE MISS MERGING [patent_app_type] => utility [patent_app_number] => 17/828189 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18316695 [patent_doc_number] => 11630776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Methods and systems for fast allocation of fragmented caches [patent_app_type] => utility [patent_app_number] => 17/827209 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19275972 [patent_doc_number] => 12026100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Method and system for low latency data management [patent_app_type] => utility [patent_app_number] => 17/825707 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17839658 [patent_doc_number] => 20220276963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => PREFETCH BUFFER OF MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/748726 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17992007 [patent_doc_number] => 20220358044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => STORE-TO-LOAD FORWARDING CORRECTNESS CHECKS USING PHYSICAL ADDRESS PROXIES STORED IN LOAD QUEUE ENTRIES [patent_app_type] => utility [patent_app_number] => 17/747513 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 58403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19327931 [patent_doc_number] => 12045619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Store-to-load forwarding correctness checks at store instruction commit [patent_app_type] => utility [patent_app_number] => 17/747670 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 68 [patent_no_of_words] => 58012 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19413313 [patent_doc_number] => 12079129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Using physical address proxies to accomplish penalty-less processing of load/store instructions whose data straddles cache line address boundaries [patent_app_type] => utility [patent_app_number] => 17/747749 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 39 [patent_no_of_words] => 41591 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19327931 [patent_doc_number] => 12045619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Store-to-load forwarding correctness checks at store instruction commit [patent_app_type] => utility [patent_app_number] => 17/747670 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 68 [patent_no_of_words] => 58012 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19413313 [patent_doc_number] => 12079129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Using physical address proxies to accomplish penalty-less processing of load/store instructions whose data straddles cache line address boundaries [patent_app_type] => utility [patent_app_number] => 17/747749 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 39 [patent_no_of_words] => 41591 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19327931 [patent_doc_number] => 12045619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Store-to-load forwarding correctness checks at store instruction commit [patent_app_type] => utility [patent_app_number] => 17/747670 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 68 [patent_no_of_words] => 58012 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19327931 [patent_doc_number] => 12045619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Store-to-load forwarding correctness checks at store instruction commit [patent_app_type] => utility [patent_app_number] => 17/747670 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 68 [patent_no_of_words] => 58012 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19413313 [patent_doc_number] => 12079129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Using physical address proxies to accomplish penalty-less processing of load/store instructions whose data straddles cache line address boundaries [patent_app_type] => utility [patent_app_number] => 17/747749 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 39 [patent_no_of_words] => 41591 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19413313 [patent_doc_number] => 12079129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Using physical address proxies to accomplish penalty-less processing of load/store instructions whose data straddles cache line address boundaries [patent_app_type] => utility [patent_app_number] => 17/747749 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 39 [patent_no_of_words] => 41591 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19413310 [patent_doc_number] => 12079126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Unforwardable load instruction re-execution eligibility based on cache update by identified store instruction [patent_app_type] => utility [patent_app_number] => 17/747703 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 68 [patent_no_of_words] => 57984 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747703 [rel_patent_id] =>[rel_patent_doc_number] =>)