Search

Idowu O. Osifade

Examiner (ID: 7639, Phone: (571)272-0864 , Office: P/2677 )

Most Active Art Unit
2666
Art Unit(s)
2677, 2673, 2666, 2675, 2661
Total Applications
829
Issued Applications
666
Pending Applications
62
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6153711 [patent_doc_number] => 20110156224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'Circuit-substrate laminated module and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 12/926288 [patent_app_country] => US [patent_app_date] => 2010-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12947 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20110156224.pdf [firstpage_image] =>[orig_patent_app_number] => 12926288 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/926288
Circular shield of a circuit-substrate laminated module and electronic apparatus Nov 7, 2010 Issued
Array ( [id] => 8180001 [patent_doc_number] => 20120112207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'METHOD TO REDUCE GROUND-PLANE POISONING OF EXTREMELY-THIN SOI (ETSOI) LAYER WITH THIN BURIED OXIDE' [patent_app_type] => utility [patent_app_number] => 12/941771 [patent_app_country] => US [patent_app_date] => 2010-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4032 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20120112207.pdf [firstpage_image] =>[orig_patent_app_number] => 12941771 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/941771
Method to reduce ground-plane poisoning of extremely-thin SOI (ETSOI) layer with thin buried oxide Nov 7, 2010 Issued
Array ( [id] => 8643210 [patent_doc_number] => 08368198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Stacked package of semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/941640 [patent_app_country] => US [patent_app_date] => 2010-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 6454 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12941640 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/941640
Stacked package of semiconductor device Nov 7, 2010 Issued
Array ( [id] => 5996488 [patent_doc_number] => 20110114927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'METHOD OF MANUFACTURING ORGANIC EL DISPLAY UNIT AND ORGANIC EL DISPLAY UNIT' [patent_app_type] => utility [patent_app_number] => 12/941463 [patent_app_country] => US [patent_app_date] => 2010-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15028 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20110114927.pdf [firstpage_image] =>[orig_patent_app_number] => 12941463 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/941463
Method of manufacturing organic EL display unit and organic EL display unit Nov 7, 2010 Issued
Array ( [id] => 6052119 [patent_doc_number] => 20110108840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/941930 [patent_app_country] => US [patent_app_date] => 2010-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4314 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20110108840.pdf [firstpage_image] =>[orig_patent_app_number] => 12941930 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/941930
Organic light emitting diode display device with different configurations of switching and driving transistors Nov 7, 2010 Issued
Array ( [id] => 6074910 [patent_doc_number] => 20110140068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'RESISTANCE-CHANGE MEMORY CELL ARRAY' [patent_app_type] => utility [patent_app_number] => 12/941434 [patent_app_country] => US [patent_app_date] => 2010-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20110140068.pdf [firstpage_image] =>[orig_patent_app_number] => 12941434 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/941434
Resistance-change memory cell array Nov 7, 2010 Issued
Array ( [id] => 8675351 [patent_doc_number] => 08383464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Method for producing field effect transistors with a back gate and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/941562 [patent_app_country] => US [patent_app_date] => 2010-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 4728 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12941562 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/941562
Method for producing field effect transistors with a back gate and semiconductor device Nov 7, 2010 Issued
Array ( [id] => 8653476 [patent_doc_number] => 08373226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-12 [patent_title] => 'Semiconductor device including a Trench-Gate Fin-FET' [patent_app_type] => utility [patent_app_number] => 12/869214 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 116 [patent_no_of_words] => 5750 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12869214 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/869214
Semiconductor device including a Trench-Gate Fin-FET Aug 25, 2010 Issued
Array ( [id] => 9140818 [patent_doc_number] => 08581282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Lighting emitting diode device with directivity and coherency and manufacturing method for providing light with directivity and coherency' [patent_app_type] => utility [patent_app_number] => 12/868961 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2431 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12868961 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/868961
Lighting emitting diode device with directivity and coherency and manufacturing method for providing light with directivity and coherency Aug 25, 2010 Issued
Array ( [id] => 8664882 [patent_doc_number] => 08378344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Light-emitting device with plural kinds of thin film transistors and circuits over one substrate' [patent_app_type] => utility [patent_app_number] => 12/869327 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 34 [patent_no_of_words] => 27689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12869327 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/869327
Light-emitting device with plural kinds of thin film transistors and circuits over one substrate Aug 25, 2010 Issued
Array ( [id] => 9530640 [patent_doc_number] => 08754516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-17 [patent_title] => 'Bumpless build-up layer package with pre-stacked microelectronic devices' [patent_app_type] => utility [patent_app_number] => 12/868816 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2765 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12868816 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/868816
Bumpless build-up layer package with pre-stacked microelectronic devices Aug 25, 2010 Issued
Array ( [id] => 6003919 [patent_doc_number] => 20110057186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'TRANSISTOR AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/869278 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 17445 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20110057186.pdf [firstpage_image] =>[orig_patent_app_number] => 12869278 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/869278
Transistor having oxide semiconductor layer and display utilizing the same Aug 25, 2010 Issued
Array ( [id] => 6003869 [patent_doc_number] => 20110057168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => '3-TERMINAL ELECTRONIC DEVICE AND 2-TERMINAL ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 12/868902 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7746 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20110057168.pdf [firstpage_image] =>[orig_patent_app_number] => 12868902 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/868902
3-terminal electronic device and 2-terminal electronic device including an active layer including nanosheets Aug 25, 2010 Issued
Array ( [id] => 6021402 [patent_doc_number] => 20110049728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'METHOD TO PERFORM ELECTRICAL TESTING AND ASSEMBLY OF ELECTRONIC DEVICES' [patent_app_type] => utility [patent_app_number] => 12/869377 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 11852 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20110049728.pdf [firstpage_image] =>[orig_patent_app_number] => 12869377 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/869377
Electronic devices with extended metallization layer on a passivation layer Aug 25, 2010 Issued
Array ( [id] => 8352544 [patent_doc_number] => 08247874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Depletion MOS transistor and charging arrangement' [patent_app_type] => utility [patent_app_number] => 12/868918 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 10011 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12868918 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/868918
Depletion MOS transistor and charging arrangement Aug 25, 2010 Issued
Array ( [id] => 6042278 [patent_doc_number] => 20110204355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'ZINC OXIDE BASED SUBSTRATE AND METHOD FOR MANUFACTURING ZINC OXIDE BASED SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/869227 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6322 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20110204355.pdf [firstpage_image] =>[orig_patent_app_number] => 12869227 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/869227
ZINC OXIDE BASED SUBSTRATE AND METHOD FOR MANUFACTURING ZINC OXIDE BASED SUBSTRATE Aug 25, 2010 Abandoned
Array ( [id] => 7762092 [patent_doc_number] => 08114730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Shared contact structure, semiconductor device and method of fabricating the semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/805226 [patent_app_country] => US [patent_app_date] => 2010-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 8079 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/114/08114730.pdf [firstpage_image] =>[orig_patent_app_number] => 12805226 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/805226
Shared contact structure, semiconductor device and method of fabricating the semiconductor device Jul 19, 2010 Issued
Array ( [id] => 6417444 [patent_doc_number] => 20100276808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'SURFACE MOUNTING ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/835491 [patent_app_country] => US [patent_app_date] => 2010-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3848 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20100276808.pdf [firstpage_image] =>[orig_patent_app_number] => 12835491 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/835491
Electronic component for surface mounting Jul 12, 2010 Issued
Array ( [id] => 7545336 [patent_doc_number] => 08053307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Method of fabricating semiconductor device with cell epitaxial layers partially overlap buried cell gate electrode' [patent_app_type] => utility [patent_app_number] => 12/662393 [patent_app_country] => US [patent_app_date] => 2010-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 6259 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/053/08053307.pdf [firstpage_image] =>[orig_patent_app_number] => 12662393 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662393
Method of fabricating semiconductor device with cell epitaxial layers partially overlap buried cell gate electrode Apr 13, 2010 Issued
Array ( [id] => 8200733 [patent_doc_number] => 08187962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Self aligned silicided contacts' [patent_app_type] => utility [patent_app_number] => 12/754294 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 44 [patent_no_of_words] => 7912 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/187/08187962.pdf [firstpage_image] =>[orig_patent_app_number] => 12754294 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754294
Self aligned silicided contacts Apr 4, 2010 Issued
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