Search

Idriss N. Alrobaye

Supervisory Patent Examiner (ID: 8005, Phone: (571)270-1023 , Office: P/2181 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2181
Total Applications
289
Issued Applications
199
Pending Applications
18
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5036562 [patent_doc_number] => 20070101101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Microprocessor' [patent_app_type] => utility [patent_app_number] => 11/584515 [patent_app_country] => US [patent_app_date] => 2006-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11146 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20070101101.pdf [firstpage_image] =>[orig_patent_app_number] => 11584515 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/584515
Microprocessor Oct 22, 2006 Abandoned
Array ( [id] => 7521020 [patent_doc_number] => 07975128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Apparatuses and programs for implementing a forwarding function' [patent_app_type] => utility [patent_app_number] => 12/161124 [patent_app_country] => US [patent_app_date] => 2006-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 10369 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/975/07975128.pdf [firstpage_image] =>[orig_patent_app_number] => 12161124 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/161124
Apparatuses and programs for implementing a forwarding function Oct 15, 2006 Issued
Array ( [id] => 5173567 [patent_doc_number] => 20070074006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method and apparatus for early load retirement in a processor system' [patent_app_type] => utility [patent_app_number] => 11/526568 [patent_app_country] => US [patent_app_date] => 2006-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6633 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20070074006.pdf [firstpage_image] =>[orig_patent_app_number] => 11526568 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/526568
Method and apparatus for early load retirement in a processor system Sep 25, 2006 Issued
Array ( [id] => 8285672 [patent_doc_number] => 08219785 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-07-10 [patent_title] => 'Adapter allowing unaligned access to memory' [patent_app_type] => utility [patent_app_number] => 11/527201 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6360 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11527201 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/527201
Adapter allowing unaligned access to memory Sep 24, 2006 Issued
Array ( [id] => 206463 [patent_doc_number] => 07634644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-15 [patent_title] => 'Effective elimination of delay slot handling from a front section of a processor pipeline' [patent_app_type] => utility [patent_app_number] => 11/534125 [patent_app_country] => US [patent_app_date] => 2006-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3717 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/634/07634644.pdf [firstpage_image] =>[orig_patent_app_number] => 11534125 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/534125
Effective elimination of delay slot handling from a front section of a processor pipeline Sep 20, 2006 Issued
Array ( [id] => 5195260 [patent_doc_number] => 20070083745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Data processor' [patent_app_type] => utility [patent_app_number] => 11/520420 [patent_app_country] => US [patent_app_date] => 2006-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 16446 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20070083745.pdf [firstpage_image] =>[orig_patent_app_number] => 11520420 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/520420
Data processor Sep 11, 2006 Abandoned
Array ( [id] => 5058629 [patent_doc_number] => 20070061551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Computer Processor Architecture Comprising Operand Stack and Addressable Registers' [patent_app_type] => utility [patent_app_number] => 11/470732 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061551.pdf [firstpage_image] =>[orig_patent_app_number] => 11470732 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/470732
Computer Processor Architecture Comprising Operand Stack and Addressable Registers Sep 6, 2006 Abandoned
Array ( [id] => 4590963 [patent_doc_number] => 07827392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Sliding-window, block-based branch target address cache' [patent_app_type] => utility [patent_app_number] => 11/422186 [patent_app_country] => US [patent_app_date] => 2006-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3903 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/827/07827392.pdf [firstpage_image] =>[orig_patent_app_number] => 11422186 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/422186
Sliding-window, block-based branch target address cache Jun 4, 2006 Issued
Array ( [id] => 809977 [patent_doc_number] => 07421566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-02 [patent_title] => 'Implementing instruction set architectures with non-contiguous register file specifiers' [patent_app_type] => utility [patent_app_number] => 11/446020 [patent_app_country] => US [patent_app_date] => 2006-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 28 [patent_no_of_words] => 15794 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/421/07421566.pdf [firstpage_image] =>[orig_patent_app_number] => 11446020 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/446020
Implementing instruction set architectures with non-contiguous register file specifiers Jun 1, 2006 Issued
Array ( [id] => 5030003 [patent_doc_number] => 20070271450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Method and system for enhanced thread synchronization and coordination' [patent_app_type] => utility [patent_app_number] => 11/436292 [patent_app_country] => US [patent_app_date] => 2006-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6907 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20070271450.pdf [firstpage_image] =>[orig_patent_app_number] => 11436292 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/436292
Method and system for enhanced thread synchronization and coordination May 16, 2006 Abandoned
Array ( [id] => 5030000 [patent_doc_number] => 20070271447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'EFFICIENT TRANSFER OF BRANCH INFORMATION' [patent_app_type] => utility [patent_app_number] => 11/383688 [patent_app_country] => US [patent_app_date] => 2006-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5007 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20070271447.pdf [firstpage_image] =>[orig_patent_app_number] => 11383688 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/383688
Efficient transfer of branch information May 15, 2006 Issued
Array ( [id] => 5734627 [patent_doc_number] => 20060259744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Method for information processing' [patent_app_type] => utility [patent_app_number] => 11/430824 [patent_app_country] => US [patent_app_date] => 2006-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 113 [patent_figures_cnt] => 113 [patent_no_of_words] => 46027 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20060259744.pdf [firstpage_image] =>[orig_patent_app_number] => 11430824 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/430824
Method for information processing May 9, 2006 Abandoned
Array ( [id] => 5047554 [patent_doc_number] => 20070266228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'BLOCK-BASED BRANCH TARGET ADDRESS CACHE' [patent_app_type] => utility [patent_app_number] => 11/382527 [patent_app_country] => US [patent_app_date] => 2006-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2787 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20070266228.pdf [firstpage_image] =>[orig_patent_app_number] => 11382527 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/382527
BLOCK-BASED BRANCH TARGET ADDRESS CACHE May 9, 2006 Abandoned
Array ( [id] => 272274 [patent_doc_number] => 07565514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Parallel condition code generation for SIMD operations' [patent_app_type] => utility [patent_app_number] => 11/413255 [patent_app_country] => US [patent_app_date] => 2006-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/565/07565514.pdf [firstpage_image] =>[orig_patent_app_number] => 11413255 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/413255
Parallel condition code generation for SIMD operations Apr 27, 2006 Issued
Array ( [id] => 5734629 [patent_doc_number] => 20060259746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Microprocessor and control method thereof' [patent_app_type] => utility [patent_app_number] => 11/409996 [patent_app_country] => US [patent_app_date] => 2006-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4509 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20060259746.pdf [firstpage_image] =>[orig_patent_app_number] => 11409996 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/409996
Microprocessor with a register selectively storing unaligned load instructions and control method thereof Apr 24, 2006 Issued
Array ( [id] => 856283 [patent_doc_number] => 07380104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-27 [patent_title] => 'Method and apparatus for back to back issue of dependent instructions in an out of order issue queue' [patent_app_type] => utility [patent_app_number] => 11/380078 [patent_app_country] => US [patent_app_date] => 2006-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4008 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/380/07380104.pdf [firstpage_image] =>[orig_patent_app_number] => 11380078 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/380078
Method and apparatus for back to back issue of dependent instructions in an out of order issue queue Apr 24, 2006 Issued
Array ( [id] => 198467 [patent_doc_number] => 07636835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-22 [patent_title] => 'Coupling data in a parallel processing environment' [patent_app_type] => utility [patent_app_number] => 11/404658 [patent_app_country] => US [patent_app_date] => 2006-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 26244 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/636/07636835.pdf [firstpage_image] =>[orig_patent_app_number] => 11404658 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/404658
Coupling data in a parallel processing environment Apr 13, 2006 Issued
Array ( [id] => 302012 [patent_doc_number] => 07539845 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-26 [patent_title] => 'Coupling integrated circuits in a parallel processing environment' [patent_app_type] => utility [patent_app_number] => 11/404409 [patent_app_country] => US [patent_app_date] => 2006-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 26101 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539845.pdf [firstpage_image] =>[orig_patent_app_number] => 11404409 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/404409
Coupling integrated circuits in a parallel processing environment Apr 13, 2006 Issued
Array ( [id] => 258132 [patent_doc_number] => 07577820 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-18 [patent_title] => 'Managing data in a parallel processing environment' [patent_app_type] => utility [patent_app_number] => 11/404958 [patent_app_country] => US [patent_app_date] => 2006-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 27078 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/577/07577820.pdf [firstpage_image] =>[orig_patent_app_number] => 11404958 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/404958
Managing data in a parallel processing environment Apr 13, 2006 Issued
Array ( [id] => 5836484 [patent_doc_number] => 20060248316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'SYSTEM AND METHOD FOR EXTRACTING FIELDS FROM PACKETS HAVING FIELDS SPREAD OVER MORE THAN ONE REGISTER' [patent_app_type] => utility [patent_app_number] => 11/279136 [patent_app_country] => US [patent_app_date] => 2006-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2684 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20060248316.pdf [firstpage_image] =>[orig_patent_app_number] => 11279136 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/279136
System and method for extracting fields from packets having fields spread over more than one register Apr 9, 2006 Issued
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