
Idriss N. Alrobaye
Supervisory Patent Examiner (ID: 8005, Phone: (571)270-1023 , Office: P/2181 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2183, 2181 |
| Total Applications | 289 |
| Issued Applications | 199 |
| Pending Applications | 18 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6941064
[patent_doc_number] => 20050114627
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-26
[patent_title] => 'Co-processing'
[patent_app_type] => utility
[patent_app_number] => 10/723454
[patent_app_country] => US
[patent_app_date] => 2003-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3424
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0114/20050114627.pdf
[firstpage_image] =>[orig_patent_app_number] => 10723454
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/723454 | Co-processing | Nov 25, 2003 | Abandoned |
Array
(
[id] => 7245558
[patent_doc_number] => 20050081015
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-14
[patent_title] => 'Method and apparatus for adapting write instructions for an expansion bus'
[patent_app_type] => utility
[patent_app_number] => 10/677082
[patent_app_country] => US
[patent_app_date] => 2003-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3954
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0081/20050081015.pdf
[firstpage_image] =>[orig_patent_app_number] => 10677082
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/677082 | Method and apparatus for adapting write instructions for an expansion bus | Sep 29, 2003 | Abandoned |
Array
(
[id] => 7394951
[patent_doc_number] => 20040031022
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-12
[patent_title] => 'Information processing device for multiple instruction sets with reconfigurable mechanism'
[patent_app_type] => new
[patent_app_number] => 10/608015
[patent_app_country] => US
[patent_app_date] => 2003-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5275
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0031/20040031022.pdf
[firstpage_image] =>[orig_patent_app_number] => 10608015
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/608015 | Information processing device for multiple instruction sets with reconfigurable mechanism | Jun 29, 2003 | Abandoned |
Array
(
[id] => 7282120
[patent_doc_number] => 20040064497
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-01
[patent_title] => 'Method and system of program transmission optimization using a redundant transmission sequence'
[patent_app_type] => new
[patent_app_number] => 10/361840
[patent_app_country] => US
[patent_app_date] => 2003-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 46
[patent_figures_cnt] => 46
[patent_no_of_words] => 13592
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0064/20040064497.pdf
[firstpage_image] =>[orig_patent_app_number] => 10361840
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/361840 | Method and system of program transmission optimization using a redundant transmission sequence | Feb 9, 2003 | Issued |
Array
(
[id] => 431378
[patent_doc_number] => 07269719
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-11
[patent_title] => 'Predicated execution using operand predicates'
[patent_app_type] => utility
[patent_app_number] => 10/283709
[patent_app_country] => US
[patent_app_date] => 2002-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 4923
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/269/07269719.pdf
[firstpage_image] =>[orig_patent_app_number] => 10283709
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/283709 | Predicated execution using operand predicates | Oct 29, 2002 | Issued |
Array
(
[id] => 6804266
[patent_doc_number] => 20030231660
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-18
[patent_title] => 'Bit-manipulation instructions for packet processing'
[patent_app_type] => new
[patent_app_number] => 10/172196
[patent_app_country] => US
[patent_app_date] => 2002-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9051
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0231/20030231660.pdf
[firstpage_image] =>[orig_patent_app_number] => 10172196
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/172196 | Bit-manipulation instructions for packet processing | Jun 13, 2002 | Abandoned |
Array
(
[id] => 8170774
[patent_doc_number] => 08176296
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-05-08
[patent_title] => 'Programmable microcontroller architecture'
[patent_app_type] => utility
[patent_app_number] => 10/033027
[patent_app_country] => US
[patent_app_date] => 2001-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 36
[patent_no_of_words] => 18292
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/176/08176296.pdf
[firstpage_image] =>[orig_patent_app_number] => 10033027
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/033027 | Programmable microcontroller architecture | Oct 21, 2001 | Issued |
Array
(
[id] => 48687
[patent_doc_number] => 07779236
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-08-17
[patent_title] => 'Symbolic store-load bypass'
[patent_app_type] => utility
[patent_app_number] => 09/443160
[patent_app_country] => US
[patent_app_date] => 1999-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2497
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/779/07779236.pdf
[firstpage_image] =>[orig_patent_app_number] => 09443160
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/443160 | Symbolic store-load bypass | Nov 18, 1999 | Issued |