Idriss N. Alrobaye

Array ( [id] => 7510398 [patent_doc_number] => 08037287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Error recovery following speculative execution with an instruction processing pipeline' [patent_app_type] => utility [patent_app_number] => 12/076165 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5655 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/037/08037287.pdf [firstpage_image] =>[orig_patent_app_number] => 12076165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4868962 [patent_doc_number] => 20080148021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'High Frequency Stall Design' [patent_app_type] => utility [patent_app_number] => 12/036704 [patent_app_country] => US [patent_app_date] => 2008-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6327 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148021.pdf [firstpage_image] =>[orig_patent_app_number] => 12036704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8208003 [patent_doc_number] => 08190855 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-29 [patent_title] => 'Coupling data for interrupt processing in a parallel processing environment' [patent_app_type] => utility [patent_app_number] => 12/036918 [patent_app_country] => US [patent_app_date] => 2008-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 26255 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/190/08190855.pdf [firstpage_image] =>[orig_patent_app_number] => 12036918 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5393359 [patent_doc_number] => 20090210672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'System and Method for Resolving Issue Conflicts of Load Instructions' [patent_app_type] => utility [patent_app_number] => 12/033111 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210672.pdf [firstpage_image] =>[orig_patent_app_number] => 12033111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5393360 [patent_doc_number] => 20090210673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'System and Method for Prioritizing Compare Instructions' [patent_app_type] => utility [patent_app_number] => 12/033122 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8908 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210673.pdf [firstpage_image] =>[orig_patent_app_number] => 12033122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5393364 [patent_doc_number] => 20090210677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'System and Method for Optimization Within a Group Priority Issue Schema for a Cascaded Pipeline' [patent_app_type] => utility [patent_app_number] => 12/033140 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210677.pdf [firstpage_image] =>[orig_patent_app_number] => 12033140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4448948 [patent_doc_number] => 07865700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'System and method for prioritizing store instructions' [patent_app_type] => utility [patent_app_number] => 12/033052 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8481 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865700.pdf [firstpage_image] =>[orig_patent_app_number] => 12033052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4614149 [patent_doc_number] => 07996654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'System and method for optimization within a group priority issue schema for a cascaded pipeline' [patent_app_type] => utility [patent_app_number] => 12/033100 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7584 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/996/07996654.pdf [firstpage_image] =>[orig_patent_app_number] => 12033100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4600635 [patent_doc_number] => 07984270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'System and method for prioritizing arithmetic instructions' [patent_app_type] => utility [patent_app_number] => 12/033047 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8305 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/984/07984270.pdf [firstpage_image] =>[orig_patent_app_number] => 12033047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5393363 [patent_doc_number] => 20090210676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'System and Method for the Scheduling of Load Instructions Within a Group Priority Issue Schema for a Cascaded Pipeline' [patent_app_type] => utility [patent_app_number] => 12/033085 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210676.pdf [firstpage_image] =>[orig_patent_app_number] => 12033085 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4486510 [patent_doc_number] => 07870368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'System and method for prioritizing branch instructions' [patent_app_type] => utility [patent_app_number] => 12/033127 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8000 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/870/07870368.pdf [firstpage_image] =>[orig_patent_app_number] => 12033127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4747265 [patent_doc_number] => 20080091867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Shared interrupt controller for a multi-threaded processor' [patent_app_type] => utility [patent_app_number] => 11/954615 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6459 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20080091867.pdf [firstpage_image] =>[orig_patent_app_number] => 11954615 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4836590 [patent_doc_number] => 20080133887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Data processing apparatus of high speed process using memory of low speed and low power consumption' [patent_app_type] => utility [patent_app_number] => 11/987704 [patent_app_country] => US [patent_app_date] => 2007-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8421 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20080133887.pdf [firstpage_image] =>[orig_patent_app_number] => 11987704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4602841 [patent_doc_number] => 07979685 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-12 [patent_title] => 'Multiple instruction execution mode resource-constrained device' [patent_app_type] => utility [patent_app_number] => 11/998054 [patent_app_country] => US [patent_app_date] => 2007-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 30 [patent_no_of_words] => 17018 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/979/07979685.pdf [firstpage_image] =>[orig_patent_app_number] => 11998054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5280661 [patent_doc_number] => 20090132793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'System and Method of Selectively Accessing a Register File' [patent_app_type] => utility [patent_app_number] => 11/943190 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7197 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20090132793.pdf [firstpage_image] =>[orig_patent_app_number] => 11943190 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8536845 [patent_doc_number] => RE043825 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2012-11-20 [patent_title] => 'System and method for data forwarding in a programmable multiple network processor environment' [patent_app_type] => reissue [patent_app_number] => 11/942275 [patent_app_country] => US [patent_app_date] => 2007-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 15399 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11942275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4586505 [patent_doc_number] => 07849292 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-07 [patent_title] => 'Flag optimization of a trace' [patent_app_type] => utility [patent_app_number] => 11/941900 [patent_app_country] => US [patent_app_date] => 2007-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 21 [patent_no_of_words] => 26085 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/849/07849292.pdf [firstpage_image] =>[orig_patent_app_number] => 11941900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4836582 [patent_doc_number] => 20080133881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Array of processing elements with local registers' [patent_app_type] => utility [patent_app_number] => 11/985229 [patent_app_country] => US [patent_app_date] => 2007-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4335 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20080133881.pdf [firstpage_image] =>[orig_patent_app_number] => 11985229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 128042 [patent_doc_number] => 07707398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'System and method for speculative global history prediction updating' [patent_app_type] => utility [patent_app_number] => 11/985025 [patent_app_country] => US [patent_app_date] => 2007-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4795 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/707/07707398.pdf [firstpage_image] =>[orig_patent_app_number] => 11985025 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4836588 [patent_doc_number] => 20080133885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'HIERARCHICAL MULTI-THREADING PROCESSOR' [patent_app_type] => utility [patent_app_number] => 11/932874 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 20789 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20080133885.pdf [firstpage_image] =>[orig_patent_app_number] => 11932874 [rel_patent_id] =>[rel_patent_doc_number] =>)