Search

Idriss N. Alrobaye

Supervisory Patent Examiner (ID: 8005, Phone: (571)270-1023 , Office: P/2181 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2181
Total Applications
289
Issued Applications
199
Pending Applications
18
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4836584 [patent_doc_number] => 20080133883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'HIERARCHICAL STORE BUFFER' [patent_app_type] => utility [patent_app_number] => 11/932864 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 20748 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20080133883.pdf [firstpage_image] =>[orig_patent_app_number] => 11932864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/932864
Hierarchical store buffer having segmented partitions Oct 30, 2007 Issued
Array ( [id] => 8460866 [patent_doc_number] => 08296550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Hierarchical register file with operand capture ports' [patent_app_type] => utility [patent_app_number] => 11/932832 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 20863 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 420 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11932832 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/932832
Hierarchical register file with operand capture ports Oct 30, 2007 Issued
Array ( [id] => 4836592 [patent_doc_number] => 20080133889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'HIERARCHICAL INSTRUCTION SCHEDULER' [patent_app_type] => utility [patent_app_number] => 11/932801 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 20789 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20080133889.pdf [firstpage_image] =>[orig_patent_app_number] => 11932801 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/932801
Hierarchical instruction scheduler facilitating instruction replay Oct 30, 2007 Issued
Array ( [id] => 8208025 [patent_doc_number] => 08190864 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-29 [patent_title] => 'APIC implementation for a highly-threaded x86 processor' [patent_app_type] => utility [patent_app_number] => 11/924491 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4679 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/190/08190864.pdf [firstpage_image] =>[orig_patent_app_number] => 11924491 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/924491
APIC implementation for a highly-threaded x86 processor Oct 24, 2007 Issued
Array ( [id] => 4787684 [patent_doc_number] => 20080141013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'DIGITAL PROCESSOR WITH CONTROL MEANS FOR THE EXECUTION OF NESTED LOOPS' [patent_app_type] => utility [patent_app_number] => 11/923984 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4760 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20080141013.pdf [firstpage_image] =>[orig_patent_app_number] => 11923984 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/923984
DIGITAL PROCESSOR WITH CONTROL MEANS FOR THE EXECUTION OF NESTED LOOPS Oct 24, 2007 Abandoned
Array ( [id] => 4486516 [patent_doc_number] => 07870369 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-11 [patent_title] => 'Abort prioritization in a trace-based processor' [patent_app_type] => utility [patent_app_number] => 11/923640 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 25 [patent_no_of_words] => 32751 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/870/07870369.pdf [firstpage_image] =>[orig_patent_app_number] => 11923640 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/923640
Abort prioritization in a trace-based processor Oct 23, 2007 Issued
Array ( [id] => 47716 [patent_doc_number] => 07783863 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-24 [patent_title] => 'Graceful degradation in a trace-based processor' [patent_app_type] => utility [patent_app_number] => 11/923638 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 25 [patent_no_of_words] => 32740 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 400 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/783/07783863.pdf [firstpage_image] =>[orig_patent_app_number] => 11923638 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/923638
Graceful degradation in a trace-based processor Oct 23, 2007 Issued
Array ( [id] => 4653332 [patent_doc_number] => 20080040589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'PROCESSOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/875431 [patent_app_country] => US [patent_app_date] => 2007-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 18069 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040589.pdf [firstpage_image] =>[orig_patent_app_number] => 11875431 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/875431
Processor device for out-of-order processing having reservation stations utilizing multiplexed arithmetic pipelines Oct 18, 2007 Issued
Array ( [id] => 4690003 [patent_doc_number] => 20080034184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'FAULT TOLERANT CELL ARRAY ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 11/872306 [patent_app_country] => US [patent_app_date] => 2007-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 17756 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20080034184.pdf [firstpage_image] =>[orig_patent_app_number] => 11872306 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/872306
FAULT TOLERANT CELL ARRAY ARCHITECTURE Oct 14, 2007 Abandoned
Array ( [id] => 4754827 [patent_doc_number] => 20080162903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Information processing apparatus' [patent_app_type] => utility [patent_app_number] => 11/907617 [patent_app_country] => US [patent_app_date] => 2007-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162903.pdf [firstpage_image] =>[orig_patent_app_number] => 11907617 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/907617
Information processing apparatus Oct 14, 2007 Abandoned
Array ( [id] => 4653329 [patent_doc_number] => 20080040586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Predicated execution using operand predicates' [patent_app_type] => utility [patent_app_number] => 11/891294 [patent_app_country] => US [patent_app_date] => 2007-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4962 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040586.pdf [firstpage_image] =>[orig_patent_app_number] => 11891294 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/891294
Predicated execution using operand predicates Aug 8, 2007 Issued
Array ( [id] => 7682371 [patent_doc_number] => 20100242040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'SYSTEM AND METHOD OF TASK ASSIGNMENT DISTRIBUTED PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/438084 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3566 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20100242040.pdf [firstpage_image] =>[orig_patent_app_number] => 12438084 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/438084
System and method of task assignment distributed processing system Jul 22, 2007 Issued
Array ( [id] => 4590961 [patent_doc_number] => 07827391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Method and apparatus for single-stepping coherence events in a multiprocessor system under software control' [patent_app_type] => utility [patent_app_number] => 11/768857 [patent_app_country] => US [patent_app_date] => 2007-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5193 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/827/07827391.pdf [firstpage_image] =>[orig_patent_app_number] => 11768857 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/768857
Method and apparatus for single-stepping coherence events in a multiprocessor system under software control Jun 25, 2007 Issued
Array ( [id] => 5351453 [patent_doc_number] => 20090006814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Immediate and Displacement Extraction and Decode Mechanism' [patent_app_type] => utility [patent_app_number] => 11/768417 [patent_app_country] => US [patent_app_date] => 2007-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7085 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20090006814.pdf [firstpage_image] =>[orig_patent_app_number] => 11768417 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/768417
Immediate and displacement extraction and decode mechanism Jun 25, 2007 Issued
Array ( [id] => 4804730 [patent_doc_number] => 20080016319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'PROCESSOR ARCHITECTURE, FOR INSTANCE FOR MULTIMEDIA APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 11/768481 [patent_app_country] => US [patent_app_date] => 2007-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4860 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20080016319.pdf [firstpage_image] =>[orig_patent_app_number] => 11768481 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/768481
Processor architecture with processing clusters providing vector and scalar data processing capability Jun 25, 2007 Issued
Array ( [id] => 4589863 [patent_doc_number] => 07831818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Exception-based timer control' [patent_app_type] => utility [patent_app_number] => 11/765891 [patent_app_country] => US [patent_app_date] => 2007-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 7064 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/831/07831818.pdf [firstpage_image] =>[orig_patent_app_number] => 11765891 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/765891
Exception-based timer control Jun 19, 2007 Issued
Array ( [id] => 4754798 [patent_doc_number] => 20080162874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'PARALLEL DATA PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/765421 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12769 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162874.pdf [firstpage_image] =>[orig_patent_app_number] => 11765421 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/765421
PARALLEL DATA PROCESSING APPARATUS Jun 18, 2007 Abandoned
Array ( [id] => 4854535 [patent_doc_number] => 20080320278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'SYSTEM AND METHOD FOR EFFICIENT DATA TRANSMISSION IN A MULTI-PROCESSOR ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 11/765372 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4259 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20080320278.pdf [firstpage_image] =>[orig_patent_app_number] => 11765372 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/765372
System and method for efficient data transmission in a multi-processor environment Jun 18, 2007 Issued
Array ( [id] => 5212100 [patent_doc_number] => 20070250684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Central processing unit having a micro-code engine' [patent_app_type] => utility [patent_app_number] => 11/790918 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5672 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20070250684.pdf [firstpage_image] =>[orig_patent_app_number] => 11790918 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/790918
Central processing unit having a micro-code engine Apr 29, 2007 Abandoned
Array ( [id] => 106831 [patent_doc_number] => 07730280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'Methods and apparatus for independent processor node operations in a SIMD array processor' [patent_app_type] => utility [patent_app_number] => 11/736814 [patent_app_country] => US [patent_app_date] => 2007-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4717 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/730/07730280.pdf [firstpage_image] =>[orig_patent_app_number] => 11736814 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/736814
Methods and apparatus for independent processor node operations in a SIMD array processor Apr 17, 2007 Issued
Menu