
Idriss N. Alrobaye
Supervisory Patent Examiner (ID: 8005, Phone: (571)270-1023 , Office: P/2181 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2183, 2181 |
| Total Applications | 289 |
| Issued Applications | 199 |
| Pending Applications | 18 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4836584
[patent_doc_number] => 20080133883
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-05
[patent_title] => 'HIERARCHICAL STORE BUFFER'
[patent_app_type] => utility
[patent_app_number] => 11/932864
[patent_app_country] => US
[patent_app_date] => 2007-10-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/932864 | Hierarchical store buffer having segmented partitions | Oct 30, 2007 | Issued |
Array
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[patent_doc_number] => 08296550
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[patent_issue_date] => 2012-10-23
[patent_title] => 'Hierarchical register file with operand capture ports'
[patent_app_type] => utility
[patent_app_number] => 11/932832
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/932832 | Hierarchical register file with operand capture ports | Oct 30, 2007 | Issued |
Array
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[patent_doc_number] => 20080133889
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[patent_kind] => A1
[patent_issue_date] => 2008-06-05
[patent_title] => 'HIERARCHICAL INSTRUCTION SCHEDULER'
[patent_app_type] => utility
[patent_app_number] => 11/932801
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[patent_app_date] => 2007-10-31
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11932801
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/932801 | Hierarchical instruction scheduler facilitating instruction replay | Oct 30, 2007 | Issued |
Array
(
[id] => 8208025
[patent_doc_number] => 08190864
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[patent_kind] => B1
[patent_issue_date] => 2012-05-29
[patent_title] => 'APIC implementation for a highly-threaded x86 processor'
[patent_app_type] => utility
[patent_app_number] => 11/924491
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[pdf_file] => patents/08/190/08190864.pdf
[firstpage_image] =>[orig_patent_app_number] => 11924491
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/924491 | APIC implementation for a highly-threaded x86 processor | Oct 24, 2007 | Issued |
Array
(
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[patent_doc_number] => 20080141013
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[patent_title] => 'DIGITAL PROCESSOR WITH CONTROL MEANS FOR THE EXECUTION OF NESTED LOOPS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/923984 | DIGITAL PROCESSOR WITH CONTROL MEANS FOR THE EXECUTION OF NESTED LOOPS | Oct 24, 2007 | Abandoned |
Array
(
[id] => 4486516
[patent_doc_number] => 07870369
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[patent_issue_date] => 2011-01-11
[patent_title] => 'Abort prioritization in a trace-based processor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/923640 | Abort prioritization in a trace-based processor | Oct 23, 2007 | Issued |
Array
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[id] => 47716
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[patent_title] => 'Graceful degradation in a trace-based processor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/923638 | Graceful degradation in a trace-based processor | Oct 23, 2007 | Issued |
Array
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[id] => 4653332
[patent_doc_number] => 20080040589
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[patent_issue_date] => 2008-02-14
[patent_title] => 'PROCESSOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/875431
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/875431 | Processor device for out-of-order processing having reservation stations utilizing multiplexed arithmetic pipelines | Oct 18, 2007 | Issued |
Array
(
[id] => 4690003
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[firstpage_image] =>[orig_patent_app_number] => 11872306
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/872306 | FAULT TOLERANT CELL ARRAY ARCHITECTURE | Oct 14, 2007 | Abandoned |
Array
(
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[patent_title] => 'Information processing apparatus'
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[patent_app_number] => 11/907617
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[firstpage_image] =>[orig_patent_app_number] => 11907617
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/907617 | Information processing apparatus | Oct 14, 2007 | Abandoned |
Array
(
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[patent_title] => 'Predicated execution using operand predicates'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/891294 | Predicated execution using operand predicates | Aug 8, 2007 | Issued |
Array
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[id] => 7682371
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[patent_title] => 'SYSTEM AND METHOD OF TASK ASSIGNMENT DISTRIBUTED PROCESSING SYSTEM'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/438084 | System and method of task assignment distributed processing system | Jul 22, 2007 | Issued |
Array
(
[id] => 4590961
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Array
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[patent_title] => 'Immediate and Displacement Extraction and Decode Mechanism'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/768481 | Processor architecture with processing clusters providing vector and scalar data processing capability | Jun 25, 2007 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/765891 | Exception-based timer control | Jun 19, 2007 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/736814 | Methods and apparatus for independent processor node operations in a SIMD array processor | Apr 17, 2007 | Issued |