Search

Idriss N. Alrobaye

Supervisory Patent Examiner (ID: 8005, Phone: (571)270-1023 , Office: P/2181 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2181
Total Applications
289
Issued Applications
199
Pending Applications
18
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 180050 [patent_doc_number] => 07657766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Apparatus for an energy efficient clustered micro-architecture' [patent_app_type] => utility [patent_app_number] => 11/698612 [patent_app_country] => US [patent_app_date] => 2007-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6007 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/657/07657766.pdf [firstpage_image] =>[orig_patent_app_number] => 11698612 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698612
Apparatus for an energy efficient clustered micro-architecture Jan 25, 2007 Issued
Array ( [id] => 5064819 [patent_doc_number] => 20070226461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Reverse polish notation device for handling tables, and electronic integrated circuit including such a processing device' [patent_app_type] => utility [patent_app_number] => 11/657392 [patent_app_country] => US [patent_app_date] => 2007-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12347 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20070226461.pdf [firstpage_image] =>[orig_patent_app_number] => 11657392 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657392
Reverse polish notation device for handling tables, and electronic integrated circuit including such a processing device Jan 23, 2007 Abandoned
Array ( [id] => 4905555 [patent_doc_number] => 20080114969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'Instructions for efficiently accessing unaligned partial vectors' [patent_app_type] => utility [patent_app_number] => 11/655656 [patent_app_country] => US [patent_app_date] => 2007-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20080114969.pdf [firstpage_image] =>[orig_patent_app_number] => 11655656 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/655656
Instructions for efficiently accessing unaligned partial vectors Jan 17, 2007 Issued
Array ( [id] => 4754803 [patent_doc_number] => 20080162879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Methods and apparatuses for aligning and/or executing instructions' [patent_app_type] => utility [patent_app_number] => 11/648156 [patent_app_country] => US [patent_app_date] => 2006-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 14456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162879.pdf [firstpage_image] =>[orig_patent_app_number] => 11648156 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/648156
Methods and apparatuses for aligning and/or executing instructions Dec 29, 2006 Abandoned
Array ( [id] => 4754834 [patent_doc_number] => 20080162910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Asynchronous control transfer' [patent_app_type] => utility [patent_app_number] => 11/648187 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5467 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162910.pdf [firstpage_image] =>[orig_patent_app_number] => 11648187 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/648187
Asynchronous control transfer Dec 28, 2006 Issued
Array ( [id] => 38219 [patent_doc_number] => 07788473 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-31 [patent_title] => 'Prediction of data values read from memory by a microprocessor using the storage destination of a load operation' [patent_app_type] => utility [patent_app_number] => 11/646008 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 13723 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/788/07788473.pdf [firstpage_image] =>[orig_patent_app_number] => 11646008 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/646008
Prediction of data values read from memory by a microprocessor using the storage destination of a load operation Dec 25, 2006 Issued
Array ( [id] => 4585802 [patent_doc_number] => 07856548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-21 [patent_title] => 'Prediction of data values read from memory by a microprocessor using a dynamic confidence threshold' [patent_app_type] => utility [patent_app_number] => 11/645901 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 13680 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/856/07856548.pdf [firstpage_image] =>[orig_patent_app_number] => 11645901 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/645901
Prediction of data values read from memory by a microprocessor using a dynamic confidence threshold Dec 25, 2006 Issued
Array ( [id] => 4606361 [patent_doc_number] => 07987347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'System and method for implementing a zero overhead loop' [patent_app_type] => utility [patent_app_number] => 11/643998 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5509 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/987/07987347.pdf [firstpage_image] =>[orig_patent_app_number] => 11643998 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/643998
System and method for implementing a zero overhead loop Dec 21, 2006 Issued
Array ( [id] => 4616532 [patent_doc_number] => 07991985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'System and method for implementing and utilizing a zero overhead loop' [patent_app_type] => utility [patent_app_number] => 11/644000 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5207 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/991/07991985.pdf [firstpage_image] =>[orig_patent_app_number] => 11644000 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/644000
System and method for implementing and utilizing a zero overhead loop Dec 21, 2006 Issued
Array ( [id] => 313140 [patent_doc_number] => 07529918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'System and method for efficiently performing bit-field extraction and bit-field combination operations in a processor' [patent_app_type] => utility [patent_app_number] => 11/643787 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9470 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/529/07529918.pdf [firstpage_image] =>[orig_patent_app_number] => 11643787 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/643787
System and method for efficiently performing bit-field extraction and bit-field combination operations in a processor Dec 21, 2006 Issued
Array ( [id] => 4589554 [patent_doc_number] => 07861069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'System and method for handling load and/or store operations in a superscalar microprocessor' [patent_app_type] => utility [patent_app_number] => 11/640968 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10915 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/861/07861069.pdf [firstpage_image] =>[orig_patent_app_number] => 11640968 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/640968
System and method for handling load and/or store operations in a superscalar microprocessor Dec 18, 2006 Issued
Array ( [id] => 7798395 [patent_doc_number] => 08127113 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-28 [patent_title] => 'Generating hardware accelerators and processor offloads' [patent_app_type] => utility [patent_app_number] => 11/607452 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 40 [patent_no_of_words] => 12465 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/127/08127113.pdf [firstpage_image] =>[orig_patent_app_number] => 11607452 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/607452
Generating hardware accelerators and processor offloads Nov 30, 2006 Issued
Array ( [id] => 4600645 [patent_doc_number] => 07984279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'System and method for using a working global history register' [patent_app_type] => utility [patent_app_number] => 11/556244 [patent_app_country] => US [patent_app_date] => 2006-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7441 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/984/07984279.pdf [firstpage_image] =>[orig_patent_app_number] => 11556244 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/556244
System and method for using a working global history register Nov 2, 2006 Issued
Array ( [id] => 4966817 [patent_doc_number] => 20080109637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'SYSTEMS AND METHODS FOR RECONFIGURABLY MULTIPROCESSING' [patent_app_type] => utility [patent_app_number] => 11/556454 [patent_app_country] => US [patent_app_date] => 2006-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5905 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109637.pdf [firstpage_image] =>[orig_patent_app_number] => 11556454 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/556454
Systems and methods for reconfiguring on-chip multiprocessors Nov 2, 2006 Issued
Array ( [id] => 325148 [patent_doc_number] => 07519797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-14 [patent_title] => 'Hierarchical multi-precision pipeline counters' [patent_app_type] => utility [patent_app_number] => 11/556020 [patent_app_country] => US [patent_app_date] => 2006-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3794 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/519/07519797.pdf [firstpage_image] =>[orig_patent_app_number] => 11556020 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/556020
Hierarchical multi-precision pipeline counters Nov 1, 2006 Issued
Array ( [id] => 7595785 [patent_doc_number] => 07620797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Instructions for efficiently accessing unaligned vectors' [patent_app_type] => utility [patent_app_number] => 11/591804 [patent_app_country] => US [patent_app_date] => 2006-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3349 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/620/07620797.pdf [firstpage_image] =>[orig_patent_app_number] => 11591804 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/591804
Instructions for efficiently accessing unaligned vectors Oct 31, 2006 Issued
Array ( [id] => 137222 [patent_doc_number] => 07698541 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-13 [patent_title] => 'System and method for isochronous task switching via hardware scheduling' [patent_app_type] => utility [patent_app_number] => 11/590205 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4765 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698541.pdf [firstpage_image] =>[orig_patent_app_number] => 11590205 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/590205
System and method for isochronous task switching via hardware scheduling Oct 30, 2006 Issued
Array ( [id] => 137221 [patent_doc_number] => 07698540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Dynamic hardware multithreading and partitioned hardware multithreading' [patent_app_type] => utility [patent_app_number] => 11/591140 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7089 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698540.pdf [firstpage_image] =>[orig_patent_app_number] => 11591140 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/591140
Dynamic hardware multithreading and partitioned hardware multithreading Oct 30, 2006 Issued
Array ( [id] => 358491 [patent_doc_number] => 07490223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Dynamic resource allocation among master processors that require service from a coprocessor' [patent_app_type] => utility [patent_app_number] => 11/555253 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8414 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/490/07490223.pdf [firstpage_image] =>[orig_patent_app_number] => 11555253 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/555253
Dynamic resource allocation among master processors that require service from a coprocessor Oct 30, 2006 Issued
Array ( [id] => 4905725 [patent_doc_number] => 20080115139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'BARRIER-BASED ACCESS TO A SHARED RESOURCE IN A MASSIVELY PARALLEL COMPUTER SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/553613 [patent_app_country] => US [patent_app_date] => 2006-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9059 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20080115139.pdf [firstpage_image] =>[orig_patent_app_number] => 11553613 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/553613
BARRIER-BASED ACCESS TO A SHARED RESOURCE IN A MASSIVELY PARALLEL COMPUTER SYSTEM Oct 26, 2006 Abandoned
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