Search

Iftekhar A. Khan

Examiner (ID: 1905, Phone: (571)272-5699 , Office: P/2128 )

Most Active Art Unit
2128
Art Unit(s)
2128, 2146, 2187, 2123, 2127
Total Applications
630
Issued Applications
462
Pending Applications
55
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17745442 [patent_doc_number] => 11393521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Power module and a memory device [patent_app_type] => utility [patent_app_number] => 17/268239 [patent_app_country] => US [patent_app_date] => 2020-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17268239 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/268239
Power module and a memory device Feb 21, 2020 Issued
Array ( [id] => 16684155 [patent_doc_number] => 10943644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-09 [patent_title] => Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same [patent_app_type] => utility [patent_app_number] => 16/795293 [patent_app_country] => US [patent_app_date] => 2020-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16795293 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/795293
Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same Feb 18, 2020 Issued
Array ( [id] => 16668547 [patent_doc_number] => 10937805 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-02 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/794415 [patent_app_country] => US [patent_app_date] => 2020-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 10030 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16794415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/794415
Semiconductor memory device Feb 18, 2020 Issued
Array ( [id] => 16668262 [patent_doc_number] => 10937515 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-02 [patent_title] => Fuse latch circuits and related apparatuses, systems, and methods [patent_app_type] => utility [patent_app_number] => 16/794860 [patent_app_country] => US [patent_app_date] => 2020-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16794860 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/794860
Fuse latch circuits and related apparatuses, systems, and methods Feb 18, 2020 Issued
Array ( [id] => 16788967 [patent_doc_number] => 10991404 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-27 [patent_title] => Loopback strobe for a memory system [patent_app_type] => utility [patent_app_number] => 16/793979 [patent_app_country] => US [patent_app_date] => 2020-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793979 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/793979
Loopback strobe for a memory system Feb 17, 2020 Issued
Array ( [id] => 17040852 [patent_doc_number] => 20210257488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => EEPROM DEVICE WITH BOTTOM GATE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/792384 [patent_app_country] => US [patent_app_date] => 2020-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16792384 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/792384
EEPROM DEVICE WITH BOTTOM GATE STRUCTURE Feb 16, 2020 Abandoned
Array ( [id] => 16021121 [patent_doc_number] => 20200185404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => 3-Dimensional NOR Strings with Segmented Shared Source Regions [patent_app_type] => utility [patent_app_number] => 16/792808 [patent_app_country] => US [patent_app_date] => 2020-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16792808 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/792808
3-dimensional NOR strings with segmented shared source regions Feb 16, 2020 Issued
Array ( [id] => 16746504 [patent_doc_number] => 10971505 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-06 [patent_title] => Memory devices and methods of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 16/786510 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 13937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786510 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/786510
Memory devices and methods of manufacturing thereof Feb 9, 2020 Issued
Array ( [id] => 18052946 [patent_doc_number] => 11526329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/782777 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 41 [patent_no_of_words] => 17057 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16782777 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/782777
Semiconductor device Feb 4, 2020 Issued
Array ( [id] => 17010652 [patent_doc_number] => 20210241813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => METASTABLE RESISTANT LATCH [patent_app_type] => utility [patent_app_number] => 16/781763 [patent_app_country] => US [patent_app_date] => 2020-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16781763 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/781763
Metastable resistant latch Feb 3, 2020 Issued
Array ( [id] => 16964719 [patent_doc_number] => 20210216218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => SYSTEM AND METHOD FOR FACILITATING IMPROVED UTILIZATION OF NAND FLASH BASED ON PAGE-WISE OPERATION [patent_app_type] => utility [patent_app_number] => 16/741313 [patent_app_country] => US [patent_app_date] => 2020-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741313 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/741313
System and method for facilitating improved utilization of NAND flash based on page-wise operation Jan 12, 2020 Issued
Array ( [id] => 16594083 [patent_doc_number] => 10903360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-26 [patent_title] => Vertically integrated memory cells with complementary pass transistor selectors [patent_app_type] => utility [patent_app_number] => 16/741238 [patent_app_country] => US [patent_app_date] => 2020-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 43 [patent_no_of_words] => 10301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741238 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/741238
Vertically integrated memory cells with complementary pass transistor selectors Jan 12, 2020 Issued
Array ( [id] => 16479344 [patent_doc_number] => 10854297 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-01 [patent_title] => Operating method of a low current electrically erasable programmable read only memory (EEPROM) array [patent_app_type] => utility [patent_app_number] => 16/739384 [patent_app_country] => US [patent_app_date] => 2020-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4300 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 729 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16739384 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/739384
Operating method of a low current electrically erasable programmable read only memory (EEPROM) array Jan 9, 2020 Issued
Array ( [id] => 16000337 [patent_doc_number] => 20200176039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => VERTICAL DECODER [patent_app_type] => utility [patent_app_number] => 16/731948 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16731948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/731948
Vertical decoder Dec 30, 2019 Issued
Array ( [id] => 16759579 [patent_doc_number] => 10978134 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-13 [patent_title] => Method and device for refreshing memory [patent_app_type] => utility [patent_app_number] => 16/730740 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 12065 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/730740
Method and device for refreshing memory Dec 29, 2019 Issued
Array ( [id] => 16879742 [patent_doc_number] => 11029889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-08 [patent_title] => Soft bit read mode selection for non-volatile memory [patent_app_type] => utility [patent_app_number] => 16/723192 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 20364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723192 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/723192
Soft bit read mode selection for non-volatile memory Dec 19, 2019 Issued
Array ( [id] => 16495512 [patent_doc_number] => 10861559 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-08 [patent_title] => Controlled string erase for nonvolatile memory [patent_app_type] => utility [patent_app_number] => 16/722322 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5708 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16722322 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/722322
Controlled string erase for nonvolatile memory Dec 19, 2019 Issued
Array ( [id] => 16521451 [patent_doc_number] => 10872674 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-22 [patent_title] => Regulation of voltage generation systems [patent_app_type] => utility [patent_app_number] => 16/722054 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10861 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16722054 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/722054
Regulation of voltage generation systems Dec 19, 2019 Issued
Array ( [id] => 16372149 [patent_doc_number] => 10803915 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-13 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/721348 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11751 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721348 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/721348
Semiconductor devices Dec 18, 2019 Issued
Array ( [id] => 15938559 [patent_doc_number] => 20200160913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => 3D NAND MEMORY Z-DECODER [patent_app_type] => utility [patent_app_number] => 16/709322 [patent_app_country] => US [patent_app_date] => 2019-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16709322 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/709322
3D NAND memory Z-decoder Dec 9, 2019 Issued
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