
Iftekhar A. Khan
Examiner (ID: 2808, Phone: (571)272-5699 , Office: P/2128 )
| Most Active Art Unit | 2128 |
| Art Unit(s) | 2127, 2128, 2146, 2123, 2187 |
| Total Applications | 617 |
| Issued Applications | 452 |
| Pending Applications | 59 |
| Abandoned Applications | 130 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10458842
[patent_doc_number] => 20150343857
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-03
[patent_title] => 'MICRO ELECTRO MECHANICAL SYSTEM, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/730362
[patent_app_country] => US
[patent_app_date] => 2015-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 11552
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14730362
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/730362 | Micro electro mechanical system, semiconductor device, and manufacturing method thereof | Jun 3, 2015 | Issued |
Array
(
[id] => 12729367
[patent_doc_number] => 20180134956
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-17
[patent_title] => PROCESS FOR IMPROVED HALIDE MATERIALS
[patent_app_type] => utility
[patent_app_number] => 15/566061
[patent_app_country] => US
[patent_app_date] => 2015-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2120
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 13
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15566061
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/566061 | Process for improved halide materials | May 17, 2015 | Issued |
Array
(
[id] => 11460145
[patent_doc_number] => 20170054051
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-23
[patent_title] => 'ADDITIONAL TEMPERATURE TREATMENT STEP FOR THIN-FILM SOLAR CELLS'
[patent_app_type] => utility
[patent_app_number] => 15/307330
[patent_app_country] => US
[patent_app_date] => 2015-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2599
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15307330
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/307330 | ADDITIONAL TEMPERATURE TREATMENT STEP FOR THIN-FILM SOLAR CELLS | Apr 23, 2015 | Abandoned |
Array
(
[id] => 11911223
[patent_doc_number] => 09780044
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-10-03
[patent_title] => 'Transient electronic device with ion-exchanged glass treated interposer'
[patent_app_type] => utility
[patent_app_number] => 14/694132
[patent_app_country] => US
[patent_app_date] => 2015-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 24
[patent_no_of_words] => 7038
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 315
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14694132
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/694132 | Transient electronic device with ion-exchanged glass treated interposer | Apr 22, 2015 | Issued |
Array
(
[id] => 12168540
[patent_doc_number] => 09887313
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-02-06
[patent_title] => 'Method for producing differently doped semiconductors'
[patent_app_type] => utility
[patent_app_number] => 15/307689
[patent_app_country] => US
[patent_app_date] => 2015-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 7003
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 270
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15307689
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/307689 | Method for producing differently doped semiconductors | Apr 16, 2015 | Issued |
Array
(
[id] => 10537753
[patent_doc_number] => 09263388
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-16
[patent_title] => 'Overlay-tolerant via mask and reactive ion etch (RIE) technique'
[patent_app_type] => utility
[patent_app_number] => 14/688027
[patent_app_country] => US
[patent_app_date] => 2015-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 10316
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14688027
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/688027 | Overlay-tolerant via mask and reactive ion etch (RIE) technique | Apr 15, 2015 | Issued |
Array
(
[id] => 10351281
[patent_doc_number] => 20150236285
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-20
[patent_title] => 'AMBIPOLAR SYNAPTIC DEVICES'
[patent_app_type] => utility
[patent_app_number] => 14/684343
[patent_app_country] => US
[patent_app_date] => 2015-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9088
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14684343
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/684343 | Ambipolar synaptic devices | Apr 10, 2015 | Issued |
Array
(
[id] => 10073634
[patent_doc_number] => 09111999
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-18
[patent_title] => 'Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics by modified RF power ramp-up'
[patent_app_type] => utility
[patent_app_number] => 14/671027
[patent_app_country] => US
[patent_app_date] => 2015-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 6110
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14671027
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/671027 | Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics by modified RF power ramp-up | Mar 26, 2015 | Issued |
Array
(
[id] => 10151924
[patent_doc_number] => 09184221
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-11-10
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/669722
[patent_app_country] => US
[patent_app_date] => 2015-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 55
[patent_no_of_words] => 25021
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14669722
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/669722 | Method of manufacturing semiconductor device | Mar 25, 2015 | Issued |
Array
(
[id] => 10294650
[patent_doc_number] => 20150179650
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-25
[patent_title] => 'FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS'
[patent_app_type] => utility
[patent_app_number] => 14/641167
[patent_app_country] => US
[patent_app_date] => 2015-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 6549
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14641167
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/641167 | Floating body memory cell having gates favoring different conductivity type regions | Mar 5, 2015 | Issued |
Array
(
[id] => 10377960
[patent_doc_number] => 20150262967
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-09-17
[patent_title] => 'HERMETICALLY SEALED WAFER PACKAGES'
[patent_app_type] => utility
[patent_app_number] => 14/640219
[patent_app_country] => US
[patent_app_date] => 2015-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2729
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14640219
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/640219 | Hermetically sealed wafer packages | Mar 5, 2015 | Issued |
Array
(
[id] => 11918307
[patent_doc_number] => 09786498
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-10-10
[patent_title] => 'Method for the production of a nitride compound semiconductor layer'
[patent_app_type] => utility
[patent_app_number] => 15/119703
[patent_app_country] => US
[patent_app_date] => 2015-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3553
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15119703
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/119703 | Method for the production of a nitride compound semiconductor layer | Feb 11, 2015 | Issued |
Array
(
[id] => 11333789
[patent_doc_number] => 09525041
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-12-20
[patent_title] => 'Semiconductor process for forming gates with different pitches and different dimensions'
[patent_app_type] => utility
[patent_app_number] => 14/621358
[patent_app_country] => US
[patent_app_date] => 2015-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4788
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14621358
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/621358 | Semiconductor process for forming gates with different pitches and different dimensions | Feb 11, 2015 | Issued |
Array
(
[id] => 11796755
[patent_doc_number] => 09406602
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-08-02
[patent_title] => 'Electronic device'
[patent_app_type] => utility
[patent_app_number] => 14/606425
[patent_app_country] => US
[patent_app_date] => 2015-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 31
[patent_no_of_words] => 5575
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14606425
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/606425 | Electronic device | Jan 26, 2015 | Issued |
Array
(
[id] => 11918296
[patent_doc_number] => 09786487
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-10-10
[patent_title] => 'Method for coating cavities of semiconductor substrates'
[patent_app_type] => utility
[patent_app_number] => 15/118914
[patent_app_country] => US
[patent_app_date] => 2015-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 8
[patent_no_of_words] => 5284
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15118914
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/118914 | Method for coating cavities of semiconductor substrates | Jan 8, 2015 | Issued |
Array
(
[id] => 10302811
[patent_doc_number] => 20150187811
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-02
[patent_title] => 'THIN FILM TRANSISTOR ARRAY PANEL'
[patent_app_type] => utility
[patent_app_number] => 14/585336
[patent_app_country] => US
[patent_app_date] => 2014-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6220
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14585336
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/585336 | Thin film transistor array panel | Dec 29, 2014 | Issued |
Array
(
[id] => 10341806
[patent_doc_number] => 20150226811
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-13
[patent_title] => 'APPARATUS AND METHOD FOR ESTIMATING INTERNAL RESISTANCE OF BATTERY PACK'
[patent_app_type] => utility
[patent_app_number] => 14/584349
[patent_app_country] => US
[patent_app_date] => 2014-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1672
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14584349
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/584349 | APPARATUS AND METHOD FOR ESTIMATING INTERNAL RESISTANCE OF BATTERY PACK | Dec 28, 2014 | Abandoned |
Array
(
[id] => 10059989
[patent_doc_number] => 09099353
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-04
[patent_title] => 'Method and system for determining overlap process windows in semiconductors by inspection techniques'
[patent_app_type] => utility
[patent_app_number] => 14/573050
[patent_app_country] => US
[patent_app_date] => 2014-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 8026
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14573050
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/573050 | Method and system for determining overlap process windows in semiconductors by inspection techniques | Dec 16, 2014 | Issued |
Array
(
[id] => 10214331
[patent_doc_number] => 20150099323
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-09
[patent_title] => 'METHOD OF MANUFACTURING SOLAR CELL MODULE AND SOLAR CELL MODULE'
[patent_app_type] => utility
[patent_app_number] => 14/571407
[patent_app_country] => US
[patent_app_date] => 2014-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3273
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14571407
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/571407 | Method of manufacturing solar cell module and solar cell module | Dec 15, 2014 | Issued |
Array
(
[id] => 11753434
[patent_doc_number] => 09711452
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-18
[patent_title] => 'Optimized wires for resistance or electromigration'
[patent_app_type] => utility
[patent_app_number] => 14/561514
[patent_app_country] => US
[patent_app_date] => 2014-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4666
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14561514
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/561514 | Optimized wires for resistance or electromigration | Dec 4, 2014 | Issued |