Search

Iftekhar A. Khan

Examiner (ID: 2808, Phone: (571)272-5699 , Office: P/2128 )

Most Active Art Unit
2128
Art Unit(s)
2127, 2128, 2146, 2123, 2187
Total Applications
617
Issued Applications
452
Pending Applications
59
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6165953 [patent_doc_number] => 20110195555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'Techniques for FinFET Doping' [patent_app_type] => utility [patent_app_number] => 12/702803 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20110195555.pdf [firstpage_image] =>[orig_patent_app_number] => 12702803 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/702803
Techniques for FinFET doping Feb 8, 2010 Issued
Array ( [id] => 6500998 [patent_doc_number] => 20100210065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'METHOD OF MANUFACTURING SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 12/702871 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4302 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20100210065.pdf [firstpage_image] =>[orig_patent_app_number] => 12702871 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/702871
METHOD OF MANUFACTURING SOLAR CELL Feb 8, 2010 Abandoned
Array ( [id] => 6508532 [patent_doc_number] => 20100216293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'Method for Fabricating Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 12/703071 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20100216293.pdf [firstpage_image] =>[orig_patent_app_number] => 12703071 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/703071
Method for fabricating semiconductor devices Feb 8, 2010 Issued
Array ( [id] => 6165950 [patent_doc_number] => 20110195553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/701623 [patent_app_country] => US [patent_app_date] => 2010-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1032 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20110195553.pdf [firstpage_image] =>[orig_patent_app_number] => 12701623 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/701623
METHOD OF FABRICATING SEMICONDUCTOR DEVICE Feb 7, 2010 Abandoned
Array ( [id] => 8896605 [patent_doc_number] => 08476126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Gate stack for high-K/metal gate last process' [patent_app_type] => utility [patent_app_number] => 12/702012 [patent_app_country] => US [patent_app_date] => 2010-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3870 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12702012 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/702012
Gate stack for high-K/metal gate last process Feb 7, 2010 Issued
Array ( [id] => 6165941 [patent_doc_number] => 20110195548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'METHOD OF FABRICATING GATE ELECTRODE USING A TREATED HARD MASK' [patent_app_type] => utility [patent_app_number] => 12/700862 [patent_app_country] => US [patent_app_date] => 2010-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20110195548.pdf [firstpage_image] =>[orig_patent_app_number] => 12700862 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/700862
Method of fabricating gate electrode using a treated hard mask Feb 4, 2010 Issued
Array ( [id] => 6165941 [patent_doc_number] => 20110195548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'METHOD OF FABRICATING GATE ELECTRODE USING A TREATED HARD MASK' [patent_app_type] => utility [patent_app_number] => 12/700862 [patent_app_country] => US [patent_app_date] => 2010-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20110195548.pdf [firstpage_image] =>[orig_patent_app_number] => 12700862 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/700862
Method of fabricating gate electrode using a treated hard mask Feb 4, 2010 Issued
Array ( [id] => 6189152 [patent_doc_number] => 20110171827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'Three Dimensional Integration and Methods of Through Silicon Via Creation' [patent_app_type] => utility [patent_app_number] => 12/687282 [patent_app_country] => US [patent_app_date] => 2010-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 3097 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20110171827.pdf [firstpage_image] =>[orig_patent_app_number] => 12687282 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/687282
Three dimensional integration and methods of through silicon via creation Jan 13, 2010 Issued
Array ( [id] => 6183902 [patent_doc_number] => 20110168982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'NANOWIRE PIN TUNNEL FIELD EFFECT DEVICES' [patent_app_type] => utility [patent_app_number] => 12/684280 [patent_app_country] => US [patent_app_date] => 2010-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20110168982.pdf [firstpage_image] =>[orig_patent_app_number] => 12684280 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/684280
Nanowire pin tunnel field effect devices Jan 7, 2010 Issued
Array ( [id] => 5985750 [patent_doc_number] => 20110097856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'METHOD OF MANUFACTURING WAFER LEVEL PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/632611 [patent_app_country] => US [patent_app_date] => 2009-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3190 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20110097856.pdf [firstpage_image] =>[orig_patent_app_number] => 12632611 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/632611
METHOD OF MANUFACTURING WAFER LEVEL PACKAGE Dec 6, 2009 Abandoned
Array ( [id] => 9099527 [patent_doc_number] => 08563401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Method for fabricating SOI substrate' [patent_app_type] => utility [patent_app_number] => 13/127257 [patent_app_country] => US [patent_app_date] => 2009-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5376 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13127257 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/127257
Method for fabricating SOI substrate Nov 10, 2009 Issued
Array ( [id] => 6284759 [patent_doc_number] => 20100157187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'TFT LCD ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/613680 [patent_app_country] => US [patent_app_date] => 2009-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3809 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20100157187.pdf [firstpage_image] =>[orig_patent_app_number] => 12613680 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/613680
TFT LCD array substrate and manufacturing method thereof Nov 5, 2009 Issued
Array ( [id] => 9827772 [patent_doc_number] => 08937000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-20 [patent_title] => 'Chemical vapor deposition with elevated temperature gas injection' [patent_app_type] => utility [patent_app_number] => 13/128163 [patent_app_country] => US [patent_app_date] => 2009-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5670 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13128163 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/128163
Chemical vapor deposition with elevated temperature gas injection Nov 5, 2009 Issued
Array ( [id] => 8642494 [patent_doc_number] => 08367476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide' [patent_app_type] => utility [patent_app_number] => 12/579574 [patent_app_country] => US [patent_app_date] => 2009-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4437 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12579574 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/579574
Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide Oct 14, 2009 Issued
Array ( [id] => 6120853 [patent_doc_number] => 20110084369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'DEVICE INCLUDING A SEMICONDUCTOR CHIP AND A CARRIER AND FABRICATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/575532 [patent_app_country] => US [patent_app_date] => 2009-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5294 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20110084369.pdf [firstpage_image] =>[orig_patent_app_number] => 12575532 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/575532
Device including a semiconductor chip and a carrier and fabrication method Oct 7, 2009 Issued
Array ( [id] => 8571631 [patent_doc_number] => 08338276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Manufacturing method for a nanocrystal based device covered with a layer of nitride deposited by CVD' [patent_app_type] => utility [patent_app_number] => 12/570869 [patent_app_country] => US [patent_app_date] => 2009-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 5834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12570869 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/570869
Manufacturing method for a nanocrystal based device covered with a layer of nitride deposited by CVD Sep 29, 2009 Issued
Array ( [id] => 5937015 [patent_doc_number] => 20110212630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'METHOD FOR PREPARING A SELF-SUPPORTING CRYSTALLIZED SILICON THIN FILM' [patent_app_type] => utility [patent_app_number] => 13/062462 [patent_app_country] => US [patent_app_date] => 2009-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3417 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20110212630.pdf [firstpage_image] =>[orig_patent_app_number] => 13062462 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/062462
METHOD FOR PREPARING A SELF-SUPPORTING CRYSTALLIZED SILICON THIN FILM Sep 2, 2009 Abandoned
Array ( [id] => 9227372 [patent_doc_number] => 08633040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-21 [patent_title] => 'Method for synthesising semiconductor quantum dots' [patent_app_type] => utility [patent_app_number] => 13/060046 [patent_app_country] => US [patent_app_date] => 2009-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3393 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13060046 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/060046
Method for synthesising semiconductor quantum dots Aug 17, 2009 Issued
Array ( [id] => 6586821 [patent_doc_number] => 20100047955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'Interconnection system for photovoltaic modules' [patent_app_type] => utility [patent_app_number] => 12/583284 [patent_app_country] => US [patent_app_date] => 2009-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3526 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20100047955.pdf [firstpage_image] =>[orig_patent_app_number] => 12583284 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/583284
Interconnection system for photovoltaic modules Aug 17, 2009 Abandoned
Array ( [id] => 6543547 [patent_doc_number] => 20100044671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'METHODS FOR INCREASING CARBON NANO-TUBE (CNT) YIELD IN MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 12/543465 [patent_app_country] => US [patent_app_date] => 2009-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9071 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20100044671.pdf [firstpage_image] =>[orig_patent_app_number] => 12543465 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/543465
Methods for increasing carbon nano-tube (CNT) yield in memory devices Aug 17, 2009 Issued
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