Search

Iftekhar A. Khan

Examiner (ID: 2808, Phone: (571)272-5699 , Office: P/2128 )

Most Active Art Unit
2128
Art Unit(s)
2127, 2128, 2146, 2123, 2187
Total Applications
617
Issued Applications
452
Pending Applications
59
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9286075 [patent_doc_number] => 08642402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Thin film transistor manufacturing method, thin film transistor, thin film transistor substrate and image display apparatus, image display apparatus and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/526304 [patent_app_country] => US [patent_app_date] => 2008-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 33 [patent_no_of_words] => 37837 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12526304 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/526304
Thin film transistor manufacturing method, thin film transistor, thin film transistor substrate and image display apparatus, image display apparatus and semiconductor device Feb 5, 2008 Issued
Array ( [id] => 5349411 [patent_doc_number] => 20090004772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/019361 [patent_app_country] => US [patent_app_date] => 2008-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 24943 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20090004772.pdf [firstpage_image] =>[orig_patent_app_number] => 12019361 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/019361
Method of manufacturing semiconductor device Jan 23, 2008 Issued
Array ( [id] => 5432196 [patent_doc_number] => 20090166782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'WAFER PROCESSING' [patent_app_type] => utility [patent_app_number] => 11/966705 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5418 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20090166782.pdf [firstpage_image] =>[orig_patent_app_number] => 11966705 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/966705
Wafer processing Dec 27, 2007 Issued
Array ( [id] => 8469731 [patent_doc_number] => 08298909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/965016 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 4525 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11965016 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/965016
Semiconductor device and method for fabricating the same Dec 26, 2007 Issued
Array ( [id] => 5422522 [patent_doc_number] => 20090148977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'PACKAGING METHOD FOR IMAGE SENSOR IC' [patent_app_type] => utility [patent_app_number] => 11/964052 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1651 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20090148977.pdf [firstpage_image] =>[orig_patent_app_number] => 11964052 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/964052
PACKAGING METHOD FOR IMAGE SENSOR IC Dec 25, 2007 Abandoned
Array ( [id] => 4901776 [patent_doc_number] => 20080111188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'INTEGRATED CIRCUIT STRUCTURE AND METHOD OF MANUFACTURING A MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 11/964022 [patent_app_country] => US [patent_app_date] => 2007-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2217 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20080111188.pdf [firstpage_image] =>[orig_patent_app_number] => 11964022 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/964022
INTEGRATED CIRCUIT STRUCTURE AND METHOD OF MANUFACTURING A MEMORY CELL Dec 24, 2007 Abandoned
Array ( [id] => 4879820 [patent_doc_number] => 20080153203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 11/962212 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3609 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20080153203.pdf [firstpage_image] =>[orig_patent_app_number] => 11962212 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962212
SEMICONDUCTOR DEVICE MANUFACTURING METHOD Dec 20, 2007 Abandoned
Array ( [id] => 8760012 [patent_doc_number] => 08420532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/962442 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1908 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11962442 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962442
Method of manufacturing semiconductor device Dec 20, 2007 Issued
Array ( [id] => 8435445 [patent_doc_number] => 08283214 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-09 [patent_title] => 'Methods for forming nickel oxide films for use with resistive switching memory devices' [patent_app_type] => utility [patent_app_number] => 11/963656 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3406 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11963656 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/963656
Methods for forming nickel oxide films for use with resistive switching memory devices Dec 20, 2007 Issued
Array ( [id] => 4859762 [patent_doc_number] => 20080268612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'METHOD OF FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/962611 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3154 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20080268612.pdf [firstpage_image] =>[orig_patent_app_number] => 11962611 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962611
METHOD OF FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE Dec 20, 2007 Abandoned
Array ( [id] => 4887057 [patent_doc_number] => 20080261389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'METHOD OF FORMING MICRO PATTERN OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/962101 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4159 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20080261389.pdf [firstpage_image] =>[orig_patent_app_number] => 11962101 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962101
METHOD OF FORMING MICRO PATTERN OF SEMICONDUCTOR DEVICE Dec 20, 2007 Abandoned
Array ( [id] => 4880011 [patent_doc_number] => 20080153394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'METHOD FOR FABRICATING HIGHLY RELIABLE INTERCONNECTS' [patent_app_type] => utility [patent_app_number] => 11/961392 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4416 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20080153394.pdf [firstpage_image] =>[orig_patent_app_number] => 11961392 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961392
Method for fabricating highly reliable interconnects Dec 19, 2007 Issued
Array ( [id] => 4879888 [patent_doc_number] => 20080153271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'SAFE HANDLING OF LOW ENERGY, HIGH DOSE ARSENIC, PHOSPHORUS, AND BORON IMPLANTED WAFERS' [patent_app_type] => utility [patent_app_number] => 11/958541 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5057 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20080153271.pdf [firstpage_image] =>[orig_patent_app_number] => 11958541 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958541
SAFE HANDLING OF LOW ENERGY, HIGH DOSE ARSENIC, PHOSPHORUS, AND BORON IMPLANTED WAFERS Dec 17, 2007 Abandoned
Array ( [id] => 6246242 [patent_doc_number] => 20100025228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'Method for Preparing Thin GaN Layers by Implantation and Recycling of a Starting Substrate' [patent_app_type] => utility [patent_app_number] => 12/518198 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6240 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20100025228.pdf [firstpage_image] =>[orig_patent_app_number] => 12518198 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/518198
Method for preparing thin GaN layers by implantation and recycling of a starting substrate Dec 17, 2007 Issued
Array ( [id] => 5546103 [patent_doc_number] => 20090155980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Methods of Forming Trench Isolation and Methods of Forming Floating Gate Transistors' [patent_app_type] => utility [patent_app_number] => 11/958551 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4031 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20090155980.pdf [firstpage_image] =>[orig_patent_app_number] => 11958551 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958551
Methods of forming trench isolation and methods of forming floating gate transistors Dec 17, 2007 Issued
Array ( [id] => 102433 [patent_doc_number] => 07723186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer' [patent_app_type] => utility [patent_app_number] => 11/958941 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 7029 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/723/07723186.pdf [firstpage_image] =>[orig_patent_app_number] => 11958941 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958941
Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer Dec 17, 2007 Issued
Array ( [id] => 5546071 [patent_doc_number] => 20090155948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'METHODS FOR MANUFACTURING CMOS COMPATIBLE BIO-SENSORS' [patent_app_type] => utility [patent_app_number] => 11/959282 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1646 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20090155948.pdf [firstpage_image] =>[orig_patent_app_number] => 11959282 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/959282
METHODS FOR MANUFACTURING CMOS COMPATIBLE BIO-SENSORS Dec 17, 2007 Abandoned
Array ( [id] => 8270276 [patent_doc_number] => 08211779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Method for forming isolation layer in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/958381 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 5907 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11958381 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958381
Method for forming isolation layer in semiconductor device Dec 16, 2007 Issued
Array ( [id] => 4723919 [patent_doc_number] => 20080203460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'MANUFACTURING METHOD FOR A NANOCRYSTAL BASED DEVICE COVERED WITH A LAYER OF NITRIDE DEPOSITED BY CVD' [patent_app_type] => utility [patent_app_number] => 11/956902 [patent_app_country] => US [patent_app_date] => 2007-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5788 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20080203460.pdf [firstpage_image] =>[orig_patent_app_number] => 11956902 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/956902
MANUFACTURING METHOD FOR A NANOCRYSTAL BASED DEVICE COVERED WITH A LAYER OF NITRIDE DEPOSITED BY CVD Dec 13, 2007 Abandoned
Array ( [id] => 4866975 [patent_doc_number] => 20080146034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'METHOD FOR RECESS ETCHING' [patent_app_type] => utility [patent_app_number] => 11/954981 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5329 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20080146034.pdf [firstpage_image] =>[orig_patent_app_number] => 11954981 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/954981
METHOD FOR RECESS ETCHING Dec 11, 2007 Abandoned
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