
Iftekhar A. Khan
Examiner (ID: 2808, Phone: (571)272-5699 , Office: P/2128 )
| Most Active Art Unit | 2128 |
| Art Unit(s) | 2127, 2128, 2146, 2123, 2187 |
| Total Applications | 617 |
| Issued Applications | 452 |
| Pending Applications | 59 |
| Abandoned Applications | 130 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9286075
[patent_doc_number] => 08642402
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[patent_kind] => B2
[patent_issue_date] => 2014-02-04
[patent_title] => 'Thin film transistor manufacturing method, thin film transistor, thin film transistor substrate and image display apparatus, image display apparatus and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/526304
[patent_app_country] => US
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12526304
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/526304 | Thin film transistor manufacturing method, thin film transistor, thin film transistor substrate and image display apparatus, image display apparatus and semiconductor device | Feb 5, 2008 | Issued |
Array
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[patent_kind] => A1
[patent_issue_date] => 2009-01-01
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2008-01-24
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Array
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[patent_kind] => A1
[patent_issue_date] => 2009-07-02
[patent_title] => 'WAFER PROCESSING'
[patent_app_type] => utility
[patent_app_number] => 11/966705
[patent_app_country] => US
[patent_app_date] => 2007-12-28
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[patent_drawing_sheets_cnt] => 11
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[firstpage_image] =>[orig_patent_app_number] => 11966705
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/966705 | Wafer processing | Dec 27, 2007 | Issued |
Array
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[patent_doc_number] => 08298909
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[patent_issue_date] => 2012-10-30
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/965016
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[patent_app_date] => 2007-12-27
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Array
(
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[patent_title] => 'PACKAGING METHOD FOR IMAGE SENSOR IC'
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Array
(
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[patent_issue_date] => 2008-05-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/964022 | INTEGRATED CIRCUIT STRUCTURE AND METHOD OF MANUFACTURING A MEMORY CELL | Dec 24, 2007 | Abandoned |
Array
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[id] => 4879820
[patent_doc_number] => 20080153203
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[patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURING METHOD'
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[patent_app_number] => 11/962212
[patent_app_country] => US
[patent_app_date] => 2007-12-21
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[patent_drawing_sheets_cnt] => 14
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Array
(
[id] => 8760012
[patent_doc_number] => 08420532
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[patent_issue_date] => 2013-04-16
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/962442
[patent_app_country] => US
[patent_app_date] => 2007-12-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/962442 | Method of manufacturing semiconductor device | Dec 20, 2007 | Issued |
Array
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[id] => 8435445
[patent_doc_number] => 08283214
[patent_country] => US
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[patent_issue_date] => 2012-10-09
[patent_title] => 'Methods for forming nickel oxide films for use with resistive switching memory devices'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/963656 | Methods for forming nickel oxide films for use with resistive switching memory devices | Dec 20, 2007 | Issued |
Array
(
[id] => 4859762
[patent_doc_number] => 20080268612
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[patent_kind] => A1
[patent_issue_date] => 2008-10-30
[patent_title] => 'METHOD OF FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/962611
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/962611 | METHOD OF FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE | Dec 20, 2007 | Abandoned |
Array
(
[id] => 4887057
[patent_doc_number] => 20080261389
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[patent_issue_date] => 2008-10-23
[patent_title] => 'METHOD OF FORMING MICRO PATTERN OF SEMICONDUCTOR DEVICE'
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[patent_app_number] => 11/962101
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/962101 | METHOD OF FORMING MICRO PATTERN OF SEMICONDUCTOR DEVICE | Dec 20, 2007 | Abandoned |
Array
(
[id] => 4880011
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[patent_title] => 'METHOD FOR FABRICATING HIGHLY RELIABLE INTERCONNECTS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/961392 | Method for fabricating highly reliable interconnects | Dec 19, 2007 | Issued |
Array
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Array
(
[id] => 6246242
[patent_doc_number] => 20100025228
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-04
[patent_title] => 'Method for Preparing Thin GaN Layers by Implantation and Recycling of a Starting Substrate'
[patent_app_type] => utility
[patent_app_number] => 12/518198
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Array
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Array
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Array
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[patent_title] => 'METHODS FOR MANUFACTURING CMOS COMPATIBLE BIO-SENSORS'
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Array
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Array
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Array
(
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[patent_title] => 'METHOD FOR RECESS ETCHING'
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