
Igwe U. Anya
Examiner (ID: 11819)
| Most Active Art Unit | 2891 |
| Art Unit(s) | 2891, 2825, 2829 |
| Total Applications | 1779 |
| Issued Applications | 1524 |
| Pending Applications | 97 |
| Abandoned Applications | 192 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5346215
[patent_doc_number] => 20090001576
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-01
[patent_title] => 'INTERCONNECT USING LIQUID METAL'
[patent_app_type] => utility
[patent_app_number] => 11/771909
[patent_app_country] => US
[patent_app_date] => 2007-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3400
[patent_no_of_claims] => 15
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20090001576.pdf
[firstpage_image] =>[orig_patent_app_number] => 11771909
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/771909 | INTERCONNECT USING LIQUID METAL | Jun 28, 2007 | Abandoned |
Array
(
[id] => 5347699
[patent_doc_number] => 20090003060
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-01
[patent_title] => 'High density NOR flash array architecture'
[patent_app_type] => utility
[patent_app_number] => 11/823518
[patent_app_country] => US
[patent_app_date] => 2007-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => publications/A1/0003/20090003060.pdf
[firstpage_image] =>[orig_patent_app_number] => 11823518
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/823518 | High density NOR flash array architecture | Jun 27, 2007 | Issued |
Array
(
[id] => 7967917
[patent_doc_number] => 07939941
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-10
[patent_title] => 'Formation of through via before contact processing'
[patent_app_type] => utility
[patent_app_number] => 11/769559
[patent_app_country] => US
[patent_app_date] => 2007-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 5177
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[pdf_file] => patents/07/939/07939941.pdf
[firstpage_image] =>[orig_patent_app_number] => 11769559
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/769559 | Formation of through via before contact processing | Jun 26, 2007 | Issued |
Array
(
[id] => 5347664
[patent_doc_number] => 20090003025
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-01
[patent_title] => 'DUAL BIT LINE METAL LAYERS FOR NON-VOLATILE MEMORY'
[patent_app_type] => utility
[patent_app_number] => 11/768468
[patent_app_country] => US
[patent_app_date] => 2007-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
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[patent_no_of_words] => 9456
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[pdf_file] => publications/A1/0003/20090003025.pdf
[firstpage_image] =>[orig_patent_app_number] => 11768468
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/768468 | Dual bit line metal layers for non-volatile memory | Jun 25, 2007 | Issued |
Array
(
[id] => 4851051
[patent_doc_number] => 20080316793
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-25
[patent_title] => 'INTEGRATED CIRCUIT INCLUDING CONTACT CONTACTING BOTTOM AND SIDEWALL OF ELECTRODE'
[patent_app_type] => utility
[patent_app_number] => 11/766819
[patent_app_country] => US
[patent_app_date] => 2007-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => publications/A1/0316/20080316793.pdf
[firstpage_image] =>[orig_patent_app_number] => 11766819
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/766819 | INTEGRATED CIRCUIT INCLUDING CONTACT CONTACTING BOTTOM AND SIDEWALL OF ELECTRODE | Jun 21, 2007 | Abandoned |
Array
(
[id] => 8738833
[patent_doc_number] => 08410607
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-04-02
[patent_title] => 'Semiconductor memory structures'
[patent_app_type] => utility
[patent_app_number] => 11/763938
[patent_app_country] => US
[patent_app_date] => 2007-06-15
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11763938
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/763938 | Semiconductor memory structures | Jun 14, 2007 | Issued |
Array
(
[id] => 4701884
[patent_doc_number] => 20080061406
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[patent_issue_date] => 2008-03-13
[patent_title] => 'SEMICONDUCTOR PACKAGE HAVING ELECTROMAGNETIC SHIELDING PART'
[patent_app_type] => utility
[patent_app_number] => 11/760239
[patent_app_country] => US
[patent_app_date] => 2007-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => publications/A1/0061/20080061406.pdf
[firstpage_image] =>[orig_patent_app_number] => 11760239
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/760239 | SEMICONDUCTOR PACKAGE HAVING ELECTROMAGNETIC SHIELDING PART | Jun 7, 2007 | Abandoned |
Array
(
[id] => 4586689
[patent_doc_number] => 07851841
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-12-14
[patent_title] => 'Large-area nanoenabled macroelectronic substrates and uses therefor'
[patent_app_type] => utility
[patent_app_number] => 11/760382
[patent_app_country] => US
[patent_app_date] => 2007-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 55
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[patent_no_of_words] => 39618
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/851/07851841.pdf
[firstpage_image] =>[orig_patent_app_number] => 11760382
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/760382 | Large-area nanoenabled macroelectronic substrates and uses therefor | Jun 7, 2007 | Issued |
Array
(
[id] => 5196690
[patent_doc_number] => 20070296008
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-27
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/758719
[patent_app_country] => US
[patent_app_date] => 2007-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => publications/A1/0296/20070296008.pdf
[firstpage_image] =>[orig_patent_app_number] => 11758719
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/758719 | SEMICONDUCTOR DEVICE | Jun 5, 2007 | Abandoned |
Array
(
[id] => 5088936
[patent_doc_number] => 20070228575
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'WIRING MATERIAL AND WIRING BOARD USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/758279
[patent_app_country] => US
[patent_app_date] => 2007-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0228/20070228575.pdf
[firstpage_image] =>[orig_patent_app_number] => 11758279
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/758279 | WIRING MATERIAL AND WIRING BOARD USING THE SAME | Jun 4, 2007 | Abandoned |
Array
(
[id] => 7492433
[patent_doc_number] => 08030773
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-10-04
[patent_title] => 'Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy'
[patent_app_type] => utility
[patent_app_number] => 11/752999
[patent_app_country] => US
[patent_app_date] => 2007-05-24
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[pdf_file] => patents/08/030/08030773.pdf
[firstpage_image] =>[orig_patent_app_number] => 11752999
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/752999 | Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy | May 23, 2007 | Issued |
Array
(
[id] => 5043783
[patent_doc_number] => 20070262454
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[patent_issue_date] => 2007-11-15
[patent_title] => 'Semiconductor device and wiring auxiliary pattern generating method'
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[patent_app_number] => 11/798179
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[firstpage_image] =>[orig_patent_app_number] => 11798179
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/798179 | Semiconductor device and wiring auxiliary pattern generating method | May 9, 2007 | Abandoned |
Array
(
[id] => 4569119
[patent_doc_number] => 07858505
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[patent_kind] => B2
[patent_issue_date] => 2010-12-28
[patent_title] => 'Method of forming a transistor having multiple types of Schottky junctions'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/744638 | Method of forming a transistor having multiple types of Schottky junctions | May 3, 2007 | Issued |
Array
(
[id] => 256279
[patent_doc_number] => 07575952
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-18
[patent_title] => 'Manufacturing method of semiconductor device having organic semiconductor film'
[patent_app_type] => utility
[patent_app_number] => 11/797419
[patent_app_country] => US
[patent_app_date] => 2007-05-03
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[firstpage_image] =>[orig_patent_app_number] => 11797419
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/797419 | Manufacturing method of semiconductor device having organic semiconductor film | May 2, 2007 | Issued |
Array
(
[id] => 4919254
[patent_doc_number] => 20080067566
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-20
[patent_title] => 'Contact structure having conductive oxide layer, ferroelectric random access memory device employing the same and methods of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/797138
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/797138 | Contact structure having conductive oxide layer, ferroelectric random access memory device employing the same and methods of fabricating the same | Apr 30, 2007 | Abandoned |
Array
(
[id] => 5002676
[patent_doc_number] => 20070200243
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-30
[patent_title] => 'ALD FORMED TITANIUM NITRIDE FILMS'
[patent_app_type] => utility
[patent_app_number] => 11/742309
[patent_app_country] => US
[patent_app_date] => 2007-04-30
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[firstpage_image] =>[orig_patent_app_number] => 11742309
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/742309 | Titanium nitride films | Apr 29, 2007 | Issued |
Array
(
[id] => 5066702
[patent_doc_number] => 20070187803
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[patent_kind] => A1
[patent_issue_date] => 2007-08-16
[patent_title] => 'Plasma Enhanced Deposited, Fully Oxidized PSG Film'
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[patent_app_number] => 11/740038
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/740038 | Plasma Enhanced Deposited, Fully Oxidized PSG Film | Apr 24, 2007 | Abandoned |
Array
(
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Array
(
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[patent_title] => 'SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/736599 | Schottky barrier diode and method of forming a Schottky barrier diode | Apr 17, 2007 | Issued |
Array
(
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[patent_issue_date] => 2007-08-09
[patent_title] => 'Integrated Circuit Chip Utilizing Dielectric Layer Having Oriented Cylindrical Voids Formed from Carbon Nanotubes'
[patent_app_type] => utility
[patent_app_number] => 11/735988
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/735988 | Integrated Circuit Chip Utilizing Dielectric Layer Having Oriented Cylindrical Voids Formed from Carbon Nanotubes | Apr 15, 2007 | Abandoned |