
Igwe U. Anya
Examiner (ID: 11819)
| Most Active Art Unit | 2891 |
| Art Unit(s) | 2891, 2825, 2829 |
| Total Applications | 1779 |
| Issued Applications | 1524 |
| Pending Applications | 97 |
| Abandoned Applications | 192 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 204641
[patent_doc_number] => 07629267
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-08
[patent_title] => 'High stress nitride film and method for formation thereof'
[patent_app_type] => utility
[patent_app_number] => 11/370228
[patent_app_country] => US
[patent_app_date] => 2006-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 13440
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/629/07629267.pdf
[firstpage_image] =>[orig_patent_app_number] => 11370228
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/370228 | High stress nitride film and method for formation thereof | Mar 5, 2006 | Issued |
Array
(
[id] => 5129119
[patent_doc_number] => 20070205516
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-06
[patent_title] => 'Low-k dielectric layer, semiconductor device, and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/364088
[patent_app_country] => US
[patent_app_date] => 2006-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3331
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20070205516.pdf
[firstpage_image] =>[orig_patent_app_number] => 11364088
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/364088 | Low-k dielectric layer, semiconductor device, and method for fabricating the same | Feb 28, 2006 | Abandoned |
Array
(
[id] => 53898
[patent_doc_number] => 07767588
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-03
[patent_title] => 'Method for forming a deposited oxide layer'
[patent_app_type] => utility
[patent_app_number] => 11/364128
[patent_app_country] => US
[patent_app_date] => 2006-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 2178
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/767/07767588.pdf
[firstpage_image] =>[orig_patent_app_number] => 11364128
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/364128 | Method for forming a deposited oxide layer | Feb 27, 2006 | Issued |
Array
(
[id] => 573413
[patent_doc_number] => 07459361
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-02
[patent_title] => 'Semiconductor device with ferroelectric capacitor and fabrication method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/358398
[patent_app_country] => US
[patent_app_date] => 2006-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 29
[patent_no_of_words] => 6300
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/459/07459361.pdf
[firstpage_image] =>[orig_patent_app_number] => 11358398
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/358398 | Semiconductor device with ferroelectric capacitor and fabrication method thereof | Feb 21, 2006 | Issued |
Array
(
[id] => 5619521
[patent_doc_number] => 20060189055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-24
[patent_title] => 'Method of forming a composite layer, method of manufacturing a gate structure by using the method of forming the composite layer and method of manufacturing a capacitor by using the method of forming the composite layer'
[patent_app_type] => utility
[patent_app_number] => 11/356399
[patent_app_country] => US
[patent_app_date] => 2006-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9525
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0189/20060189055.pdf
[firstpage_image] =>[orig_patent_app_number] => 11356399
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/356399 | Method of forming a composite layer, method of manufacturing a gate structure by using the method of forming the composite layer and method of manufacturing a capacitor by using the method of forming the composite layer | Feb 15, 2006 | Abandoned |
Array
(
[id] => 7597268
[patent_doc_number] => 07619309
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-17
[patent_title] => 'Integrated connection arrangements'
[patent_app_type] => utility
[patent_app_number] => 11/350518
[patent_app_country] => US
[patent_app_date] => 2006-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4516
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/619/07619309.pdf
[firstpage_image] =>[orig_patent_app_number] => 11350518
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/350518 | Integrated connection arrangements | Feb 8, 2006 | Issued |
Array
(
[id] => 5669944
[patent_doc_number] => 20060175297
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-10
[patent_title] => 'Metallization method for a semiconductor device and post-CMP cleaning solution for the same'
[patent_app_type] => utility
[patent_app_number] => 11/344049
[patent_app_country] => US
[patent_app_date] => 2006-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4430
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0175/20060175297.pdf
[firstpage_image] =>[orig_patent_app_number] => 11344049
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/344049 | Metallization method for a semiconductor device and post-CMP cleaning solution for the same | Jan 31, 2006 | Abandoned |
Array
(
[id] => 5667206
[patent_doc_number] => 20060172556
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-03
[patent_title] => 'Semiconductor device having a high carbon content strain inducing film and a method of manufacture therefor'
[patent_app_type] => utility
[patent_app_number] => 11/344998
[patent_app_country] => US
[patent_app_date] => 2006-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4279
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0172/20060172556.pdf
[firstpage_image] =>[orig_patent_app_number] => 11344998
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/344998 | Semiconductor device having a high carbon content strain inducing film and a method of manufacture therefor | Jan 31, 2006 | Abandoned |
Array
(
[id] => 5691675
[patent_doc_number] => 20060151820
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-13
[patent_title] => 'Large-area nanoenabled macroelectronic substrates and uses therefor'
[patent_app_type] => utility
[patent_app_number] => 11/341711
[patent_app_country] => US
[patent_app_date] => 2006-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 52
[patent_figures_cnt] => 52
[patent_no_of_words] => 39548
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0151/20060151820.pdf
[firstpage_image] =>[orig_patent_app_number] => 11341711
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/341711 | Large-area nanoenabled macroelectronic substrates and uses therefor | Jan 29, 2006 | Abandoned |
Array
(
[id] => 5908729
[patent_doc_number] => 20060124890
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Liquid composition for forming ferroelectric thin film and process for producing ferroelectric thin film'
[patent_app_type] => utility
[patent_app_number] => 11/340548
[patent_app_country] => US
[patent_app_date] => 2006-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5430
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20060124890.pdf
[firstpage_image] =>[orig_patent_app_number] => 11340548
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/340548 | Liquid composition for forming ferroelectric thin film and process for producing ferroelectric thin film | Jan 26, 2006 | Abandoned |
Array
(
[id] => 92061
[patent_doc_number] => 07732347
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-08
[patent_title] => 'Semiconductor device and fabrication process of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/338878
[patent_app_country] => US
[patent_app_date] => 2006-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 61
[patent_no_of_words] => 10814
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/732/07732347.pdf
[firstpage_image] =>[orig_patent_app_number] => 11338878
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/338878 | Semiconductor device and fabrication process of semiconductor device | Jan 24, 2006 | Issued |
Array
(
[id] => 5649089
[patent_doc_number] => 20060134824
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-22
[patent_title] => 'P-type OFET with fluorinated channels'
[patent_app_type] => utility
[patent_app_number] => 11/337897
[patent_app_country] => US
[patent_app_date] => 2006-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4082
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0134/20060134824.pdf
[firstpage_image] =>[orig_patent_app_number] => 11337897
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/337897 | P-type OFET with fluorinated channels | Jan 22, 2006 | Issued |
Array
(
[id] => 5043732
[patent_doc_number] => 20070262403
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-15
[patent_title] => 'Semiconductor Device and Method for Manufacturing the Same'
[patent_app_type] => utility
[patent_app_number] => 11/793199
[patent_app_country] => US
[patent_app_date] => 2006-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 17099
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 15
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0262/20070262403.pdf
[firstpage_image] =>[orig_patent_app_number] => 11793199
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/793199 | Semiconductor device and method for manufacturing the same | Jan 17, 2006 | Issued |
Array
(
[id] => 233149
[patent_doc_number] => 07598576
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-10-06
[patent_title] => 'Environmentally robust passivation structures for high-voltage silicon carbide semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 11/328550
[patent_app_country] => US
[patent_app_date] => 2006-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3656
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/598/07598576.pdf
[firstpage_image] =>[orig_patent_app_number] => 11328550
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/328550 | Environmentally robust passivation structures for high-voltage silicon carbide semiconductor devices | Jan 9, 2006 | Issued |
Array
(
[id] => 5843614
[patent_doc_number] => 20060121699
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-08
[patent_title] => 'Deposition methods'
[patent_app_type] => utility
[patent_app_number] => 11/326739
[patent_app_country] => US
[patent_app_date] => 2006-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5946
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0121/20060121699.pdf
[firstpage_image] =>[orig_patent_app_number] => 11326739
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/326739 | Deposition methods | Jan 4, 2006 | Issued |
Array
(
[id] => 263636
[patent_doc_number] => 07569400
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-04
[patent_title] => 'Ferroelectric film, method of manufacturing ferroelectric film, ferroelectric capacitor, and ferroelectric memory'
[patent_app_type] => utility
[patent_app_number] => 11/316168
[patent_app_country] => US
[patent_app_date] => 2005-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 25
[patent_no_of_words] => 8898
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/569/07569400.pdf
[firstpage_image] =>[orig_patent_app_number] => 11316168
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/316168 | Ferroelectric film, method of manufacturing ferroelectric film, ferroelectric capacitor, and ferroelectric memory | Dec 21, 2005 | Issued |
Array
(
[id] => 5691738
[patent_doc_number] => 20060151883
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-13
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/312709
[patent_app_country] => US
[patent_app_date] => 2005-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 11701
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0151/20060151883.pdf
[firstpage_image] =>[orig_patent_app_number] => 11312709
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/312709 | Semiconductor integrated circuit | Dec 20, 2005 | Issued |
Array
(
[id] => 5120138
[patent_doc_number] => 20070141852
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-21
[patent_title] => 'Methods of fabricating isolation regions of semiconductor devices and structures thereof'
[patent_app_type] => utility
[patent_app_number] => 11/312878
[patent_app_country] => US
[patent_app_date] => 2005-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6192
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20070141852.pdf
[firstpage_image] =>[orig_patent_app_number] => 11312878
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/312878 | Methods of fabricating isolation regions of semiconductor devices and structures thereof | Dec 19, 2005 | Issued |
Array
(
[id] => 6558623
[patent_doc_number] => 20100059485
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-11
[patent_title] => 'MIG-MIG Welding Process'
[patent_app_type] => utility
[patent_app_number] => 11/793321
[patent_app_country] => US
[patent_app_date] => 2005-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3665
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 25
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0059/20100059485.pdf
[firstpage_image] =>[orig_patent_app_number] => 11793321
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/793321 | MIG-MIG Welding Process | Dec 18, 2005 | Abandoned |
Array
(
[id] => 5180736
[patent_doc_number] => 20070052078
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-08
[patent_title] => 'MATRIX PACKAGE SUBSTRATE STRUCTURE, CHIP PACKAGE STRUCTURE AND MOLDING PROCESS THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/164968
[patent_app_country] => US
[patent_app_date] => 2005-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2715
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0052/20070052078.pdf
[firstpage_image] =>[orig_patent_app_number] => 11164968
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/164968 | MATRIX PACKAGE SUBSTRATE STRUCTURE, CHIP PACKAGE STRUCTURE AND MOLDING PROCESS THEREOF | Dec 12, 2005 | Abandoned |