Search

Igwe U. Anya

Examiner (ID: 11819)

Most Active Art Unit
2891
Art Unit(s)
2891, 2825, 2829
Total Applications
1779
Issued Applications
1524
Pending Applications
97
Abandoned Applications
192

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7429311 [patent_doc_number] => 20040266081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Methods of forming field effect transistors including raised source/drain regions' [patent_app_type] => new [patent_app_number] => 10/832080 [patent_app_country] => US [patent_app_date] => 2004-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6138 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266081.pdf [firstpage_image] =>[orig_patent_app_number] => 10832080 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/832080
Methods of forming field effect transistors including raised source/drain regions Apr 25, 2004 Issued
Array ( [id] => 7058877 [patent_doc_number] => 20050001236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor' [patent_app_type] => utility [patent_app_number] => 10/824745 [patent_app_country] => US [patent_app_date] => 2004-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1294 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20050001236.pdf [firstpage_image] =>[orig_patent_app_number] => 10824745 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/824745
Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor Apr 14, 2004 Issued
Array ( [id] => 7442283 [patent_doc_number] => 20040185589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Semiconductor device, semiconductor laser, their manufacturing methods and etching methods' [patent_app_type] => new [patent_app_number] => 10/816929 [patent_app_country] => US [patent_app_date] => 2004-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11845 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20040185589.pdf [firstpage_image] =>[orig_patent_app_number] => 10816929 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/816929
Semiconductor device, semiconductor laser, their manufacturing methods and etching methods Apr 4, 2004 Issued
Array ( [id] => 694611 [patent_doc_number] => 07071009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'MRAM arrays with reduced bit line resistance and method to make the same' [patent_app_type] => utility [patent_app_number] => 10/816041 [patent_app_country] => US [patent_app_date] => 2004-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6414 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/071/07071009.pdf [firstpage_image] =>[orig_patent_app_number] => 10816041 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/816041
MRAM arrays with reduced bit line resistance and method to make the same Mar 31, 2004 Issued
Array ( [id] => 7252755 [patent_doc_number] => 20040259276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Process system health index and method of using the same' [patent_app_type] => new [patent_app_number] => 10/809437 [patent_app_country] => US [patent_app_date] => 2004-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6165 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20040259276.pdf [firstpage_image] =>[orig_patent_app_number] => 10809437 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/809437
Process system health index and method of using the same Mar 25, 2004 Issued
Array ( [id] => 773508 [patent_doc_number] => 07001833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Method for forming openings in low-k dielectric layers' [patent_app_type] => utility [patent_app_number] => 10/808801 [patent_app_country] => US [patent_app_date] => 2004-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5394 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/001/07001833.pdf [firstpage_image] =>[orig_patent_app_number] => 10808801 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/808801
Method for forming openings in low-k dielectric layers Mar 24, 2004 Issued
Array ( [id] => 7296426 [patent_doc_number] => 20040214375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Method of manufacturing semiconductor device, flexible substrate, and semiconductor device' [patent_app_type] => new [patent_app_number] => 10/808398 [patent_app_country] => US [patent_app_date] => 2004-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3091 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20040214375.pdf [firstpage_image] =>[orig_patent_app_number] => 10808398 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/808398
Method of manufacturing semiconductor device, flexible substrate, and semiconductor device Mar 24, 2004 Issued
Array ( [id] => 1014585 [patent_doc_number] => 06893927 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-17 [patent_title] => 'Method for making a semiconductor device with a metal gate electrode' [patent_app_type] => utility [patent_app_number] => 10/805880 [patent_app_country] => US [patent_app_date] => 2004-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3681 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/893/06893927.pdf [firstpage_image] =>[orig_patent_app_number] => 10805880 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/805880
Method for making a semiconductor device with a metal gate electrode Mar 21, 2004 Issued
Array ( [id] => 7074855 [patent_doc_number] => 20050148123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Method for fabricating self-aligned thin-film transistor' [patent_app_type] => utility [patent_app_number] => 10/805340 [patent_app_country] => US [patent_app_date] => 2004-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2333 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20050148123.pdf [firstpage_image] =>[orig_patent_app_number] => 10805340 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/805340
Method for fabricating self-aligned thin-film transistor Mar 21, 2004 Abandoned
Array ( [id] => 968890 [patent_doc_number] => 06940167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'Variable cross-section plated mushroom with stud for bumping' [patent_app_type] => utility [patent_app_number] => 10/805130 [patent_app_country] => US [patent_app_date] => 2004-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1678 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/940/06940167.pdf [firstpage_image] =>[orig_patent_app_number] => 10805130 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/805130
Variable cross-section plated mushroom with stud for bumping Mar 18, 2004 Issued
Array ( [id] => 7111242 [patent_doc_number] => 20050208698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Monitoring the deposition properties of an oled' [patent_app_type] => utility [patent_app_number] => 10/803761 [patent_app_country] => US [patent_app_date] => 2004-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4779 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20050208698.pdf [firstpage_image] =>[orig_patent_app_number] => 10803761 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/803761
Monitoring the deposition properties of an OLED Mar 17, 2004 Issued
Array ( [id] => 712112 [patent_doc_number] => 07057205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'P-type OFET with fluorinated channels' [patent_app_type] => utility [patent_app_number] => 10/802973 [patent_app_country] => US [patent_app_date] => 2004-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4080 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057205.pdf [firstpage_image] =>[orig_patent_app_number] => 10802973 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/802973
P-type OFET with fluorinated channels Mar 16, 2004 Issued
Array ( [id] => 785225 [patent_doc_number] => 06989312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Method for fabricating semiconductor optical device' [patent_app_type] => utility [patent_app_number] => 10/800680 [patent_app_country] => US [patent_app_date] => 2004-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3493 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/989/06989312.pdf [firstpage_image] =>[orig_patent_app_number] => 10800680 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/800680
Method for fabricating semiconductor optical device Mar 15, 2004 Issued
Array ( [id] => 6918253 [patent_doc_number] => 20050095814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Ultrathin form factor MEMS microphones and microspeakers' [patent_app_type] => utility [patent_app_number] => 10/800470 [patent_app_country] => US [patent_app_date] => 2004-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 5541 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20050095814.pdf [firstpage_image] =>[orig_patent_app_number] => 10800470 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/800470
Ultrathin form factor MEMS microphones and microspeakers Mar 14, 2004 Abandoned
Array ( [id] => 7406582 [patent_doc_number] => 20040175888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Scalable self-aligned dual floating gate memory cell array and methods of forming the array' [patent_app_type] => new [patent_app_number] => 10/799180 [patent_app_country] => US [patent_app_date] => 2004-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11102 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20040175888.pdf [firstpage_image] =>[orig_patent_app_number] => 10799180 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/799180
Scalable self-aligned dual floating gate memory cell array and methods of forming the array Mar 11, 2004 Issued
Array ( [id] => 773349 [patent_doc_number] => 07001793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Method of protecting microfabricated devices with protective caps' [patent_app_type] => utility [patent_app_number] => 10/791840 [patent_app_country] => US [patent_app_date] => 2004-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 4592 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/001/07001793.pdf [firstpage_image] =>[orig_patent_app_number] => 10791840 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/791840
Method of protecting microfabricated devices with protective caps Mar 3, 2004 Issued
Array ( [id] => 728301 [patent_doc_number] => 07041536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-09 [patent_title] => 'Semiconductor integrated circuit card manufacturing method, and semiconductor integrated circuit card' [patent_app_type] => utility [patent_app_number] => 10/790450 [patent_app_country] => US [patent_app_date] => 2004-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 2886 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/041/07041536.pdf [firstpage_image] =>[orig_patent_app_number] => 10790450 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/790450
Semiconductor integrated circuit card manufacturing method, and semiconductor integrated circuit card Feb 26, 2004 Issued
Array ( [id] => 690449 [patent_doc_number] => 07074673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-11 [patent_title] => 'Service programmable logic arrays with low tunnel barrier interpoly insulators' [patent_app_type] => utility [patent_app_number] => 10/788810 [patent_app_country] => US [patent_app_date] => 2004-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 13876 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/074/07074673.pdf [firstpage_image] =>[orig_patent_app_number] => 10788810 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/788810
Service programmable logic arrays with low tunnel barrier interpoly insulators Feb 26, 2004 Issued
Array ( [id] => 956176 [patent_doc_number] => 06955926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-18 [patent_title] => 'Method of fabricating data tracks for use in a magnetic shift register memory device' [patent_app_type] => utility [patent_app_number] => 10/788190 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 62 [patent_no_of_words] => 13053 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/955/06955926.pdf [firstpage_image] =>[orig_patent_app_number] => 10788190 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/788190
Method of fabricating data tracks for use in a magnetic shift register memory device Feb 24, 2004 Issued
Array ( [id] => 7465298 [patent_doc_number] => 20040166612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Fabrication of silicon-on-insulator structure using plasma immersion ion implantation' [patent_app_type] => new [patent_app_number] => 10/786410 [patent_app_country] => US [patent_app_date] => 2004-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 96 [patent_figures_cnt] => 96 [patent_no_of_words] => 43507 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20040166612.pdf [firstpage_image] =>[orig_patent_app_number] => 10786410 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/786410
Fabrication of silicon-on-insulator structure using plasma immersion ion implantation Feb 23, 2004 Issued
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