Search

Igwe U. Anya

Examiner (ID: 11819)

Most Active Art Unit
2891
Art Unit(s)
2891, 2825, 2829
Total Applications
1779
Issued Applications
1524
Pending Applications
97
Abandoned Applications
192

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6740412 [patent_doc_number] => 20030157781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Method of filling trenches' [patent_app_type] => new [patent_app_number] => 10/220800 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2401 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20030157781.pdf [firstpage_image] =>[orig_patent_app_number] => 10220800 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/220800
Method of filling trenches Nov 7, 2002 Abandoned
Array ( [id] => 1059459 [patent_doc_number] => 06852549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Ferroelectric thin film processing for ferroelectric field-effect transistor' [patent_app_type] => utility [patent_app_number] => 10/273200 [patent_app_country] => US [patent_app_date] => 2002-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2772 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/852/06852549.pdf [firstpage_image] =>[orig_patent_app_number] => 10273200 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/273200
Ferroelectric thin film processing for ferroelectric field-effect transistor Oct 16, 2002 Issued
Array ( [id] => 6669920 [patent_doc_number] => 20030114904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Semiconductor and non-semiconductor non-diffusion-governed bioelectrodes' [patent_app_type] => new [patent_app_number] => 10/261000 [patent_app_country] => US [patent_app_date] => 2002-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20030114904.pdf [firstpage_image] =>[orig_patent_app_number] => 10261000 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/261000
Semiconductor and non-semiconductor non-diffusion-governed bioelectrodes Sep 29, 2002 Issued
Array ( [id] => 7607633 [patent_doc_number] => 07098081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Semiconductor device and method of manufacturing the device' [patent_app_type] => utility [patent_app_number] => 10/490980 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4516 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/098/07098081.pdf [firstpage_image] =>[orig_patent_app_number] => 10490980 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/490980
Semiconductor device and method of manufacturing the device Sep 26, 2002 Issued
Array ( [id] => 7280931 [patent_doc_number] => 20040063308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Method for forming openings in low-k dielectric layers' [patent_app_type] => new [patent_app_number] => 10/256400 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5147 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20040063308.pdf [firstpage_image] =>[orig_patent_app_number] => 10256400 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/256400
Method for forming openings in low-k dielectric layers Sep 26, 2002 Abandoned
Array ( [id] => 1130223 [patent_doc_number] => 06787383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Light-emitting device and method for manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 10/255000 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 10665 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/787/06787383.pdf [firstpage_image] =>[orig_patent_app_number] => 10255000 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/255000
Light-emitting device and method for manufacturing the same Sep 25, 2002 Issued
Array ( [id] => 446090 [patent_doc_number] => 07253091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Process for assembling three-dimensional systems on a chip and structure thus obtained' [patent_app_type] => utility [patent_app_number] => 10/256336 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 8112 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/253/07253091.pdf [firstpage_image] =>[orig_patent_app_number] => 10256336 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/256336
Process for assembling three-dimensional systems on a chip and structure thus obtained Sep 25, 2002 Issued
Array ( [id] => 1281263 [patent_doc_number] => 06642158 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Photo-thermal induced diffusion' [patent_app_type] => B1 [patent_app_number] => 10/252304 [patent_app_country] => US [patent_app_date] => 2002-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4128 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/642/06642158.pdf [firstpage_image] =>[orig_patent_app_number] => 10252304 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/252304
Photo-thermal induced diffusion Sep 22, 2002 Issued
Array ( [id] => 6671496 [patent_doc_number] => 20030057099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'System and method for electroplating fine geometries' [patent_app_type] => new [patent_app_number] => 10/247000 [patent_app_country] => US [patent_app_date] => 2002-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3365 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20030057099.pdf [firstpage_image] =>[orig_patent_app_number] => 10247000 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/247000
System and method for electroplating fine geometries Sep 18, 2002 Issued
Array ( [id] => 1164960 [patent_doc_number] => 06756238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'Domain controlled piezoelectric single crystal and fabrication method therefor' [patent_app_type] => B2 [patent_app_number] => 10/246400 [patent_app_country] => US [patent_app_date] => 2002-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7770 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/756/06756238.pdf [firstpage_image] =>[orig_patent_app_number] => 10246400 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246400
Domain controlled piezoelectric single crystal and fabrication method therefor Sep 18, 2002 Issued
Array ( [id] => 6774353 [patent_doc_number] => 20030017691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Method for relieving bond stress in an under-bond-pad resistor' [patent_app_type] => new [patent_app_number] => 10/247253 [patent_app_country] => US [patent_app_date] => 2002-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1821 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20030017691.pdf [firstpage_image] =>[orig_patent_app_number] => 10247253 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/247253
Method for relieving bond stress in an under-bond-pad resistor Sep 17, 2002 Issued
Array ( [id] => 7465384 [patent_doc_number] => 20040053475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Method for forming a sublithographic opening in a semiconductor process' [patent_app_type] => new [patent_app_number] => 10/247400 [patent_app_country] => US [patent_app_date] => 2002-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2045 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20040053475.pdf [firstpage_image] =>[orig_patent_app_number] => 10247400 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/247400
Method for forming a sublithographic opening in a semiconductor process Sep 17, 2002 Issued
Array ( [id] => 7465432 [patent_doc_number] => 20040053484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Method of fabricating a gate structure of a field effect transistor using a hard mask' [patent_app_type] => new [patent_app_number] => 10/245130 [patent_app_country] => US [patent_app_date] => 2002-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4793 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20040053484.pdf [firstpage_image] =>[orig_patent_app_number] => 10245130 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/245130
Method of fabricating a gate structure of a field effect transistor using a hard mask Sep 15, 2002 Issued
Array ( [id] => 1037496 [patent_doc_number] => 06872645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Methods of positioning and/or orienting nanostructures' [patent_app_type] => utility [patent_app_number] => 10/239000 [patent_app_country] => US [patent_app_date] => 2002-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9496 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/872/06872645.pdf [firstpage_image] =>[orig_patent_app_number] => 10239000 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/239000
Methods of positioning and/or orienting nanostructures Sep 9, 2002 Issued
Array ( [id] => 6651341 [patent_doc_number] => 20030008488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Method for manufacturing non-volatile semiconductor memory and non-volatile semiconductor memory manufactured thereby' [patent_app_type] => new [patent_app_number] => 10/237805 [patent_app_country] => US [patent_app_date] => 2002-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9379 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20030008488.pdf [firstpage_image] =>[orig_patent_app_number] => 10237805 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/237805
Method for manufacturing non-volatile semiconductor memory and non-volatile semiconductor memory manufactured thereby Sep 9, 2002 Issued
Array ( [id] => 6829910 [patent_doc_number] => 20030180968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Method of preventing short circuits in magnetic film stacks' [patent_app_type] => new [patent_app_number] => 10/235100 [patent_app_country] => US [patent_app_date] => 2002-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7979 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20030180968.pdf [firstpage_image] =>[orig_patent_app_number] => 10235100 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/235100
Method of preventing short circuits in magnetic film stacks Sep 3, 2002 Issued
Array ( [id] => 6817943 [patent_doc_number] => 20030068901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Method for forming dual oxide layers at bottom of trench' [patent_app_type] => new [patent_app_number] => 10/232260 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20030068901.pdf [firstpage_image] =>[orig_patent_app_number] => 10232260 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/232260
Method for forming dual oxide layers at bottom of trench Aug 28, 2002 Issued
Array ( [id] => 7429428 [patent_doc_number] => 20040266099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Integrated circuit, its fabrication process and memory cell incorporating such a circuit' [patent_app_type] => new [patent_app_number] => 10/486950 [patent_app_country] => US [patent_app_date] => 2004-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4150 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266099.pdf [firstpage_image] =>[orig_patent_app_number] => 10486950 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/486950
Integrated circuit, its fabrication process and memory cell incorporating such a circuit Aug 13, 2002 Issued
Array ( [id] => 6865273 [patent_doc_number] => 20030190799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Pattern formation process for an integrated circuit substrate' [patent_app_type] => new [patent_app_number] => 10/211700 [patent_app_country] => US [patent_app_date] => 2002-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3671 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20030190799.pdf [firstpage_image] =>[orig_patent_app_number] => 10211700 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/211700
Pattern formation process for an integrated circuit substrate Aug 1, 2002 Issued
Array ( [id] => 448619 [patent_doc_number] => 07250375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-31 [patent_title] => 'Substrate processing method and material for electronic device' [patent_app_type] => utility [patent_app_number] => 10/485410 [patent_app_country] => US [patent_app_date] => 2002-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 9481 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/250/07250375.pdf [firstpage_image] =>[orig_patent_app_number] => 10485410 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/485410
Substrate processing method and material for electronic device Aug 1, 2002 Issued
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