
Phillips Iii
Examiner (ID: 1023, Phone: III ALBERT M )
| Most Active Art Unit | 2159 |
| Art Unit(s) | 2154, 2155, 2169, 2159 |
| Total Applications | 771 |
| Issued Applications | 616 |
| Pending Applications | 43 |
| Abandoned Applications | 127 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16858662
[patent_doc_number] => 20210159407
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-27
[patent_title] => RRAM STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/142591
[patent_app_country] => US
[patent_app_date] => 2021-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8465
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142591
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/142591 | RRAM structure | Jan 5, 2021 | Issued |
Array
(
[id] => 18131331
[patent_doc_number] => 11557548
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-17
[patent_title] => Package with interlocking leads and manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/137262
[patent_app_country] => US
[patent_app_date] => 2020-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 23
[patent_no_of_words] => 13296
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137262
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/137262 | Package with interlocking leads and manufacturing the same | Dec 28, 2020 | Issued |
Array
(
[id] => 17708670
[patent_doc_number] => 20220208678
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-30
[patent_title] => INSET POWER POST AND STRAP ARCHITECTURE WITH REDUCED VOLTAGE DROOP
[patent_app_type] => utility
[patent_app_number] => 17/135122
[patent_app_country] => US
[patent_app_date] => 2020-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7853
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135122
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/135122 | Inset power post and strap architecture with reduced voltage droop | Dec 27, 2020 | Issued |
Array
(
[id] => 18331812
[patent_doc_number] => 11637068
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-25
[patent_title] => Thermally and electrically conductive interconnects
[patent_app_type] => utility
[patent_app_number] => 17/121810
[patent_app_country] => US
[patent_app_date] => 2020-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 23
[patent_no_of_words] => 4194
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121810
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/121810 | Thermally and electrically conductive interconnects | Dec 14, 2020 | Issued |
Array
(
[id] => 18857419
[patent_doc_number] => 11855014
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-26
[patent_title] => Semiconductor device and method
[patent_app_type] => utility
[patent_app_number] => 17/120825
[patent_app_country] => US
[patent_app_date] => 2020-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 9728
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120825
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/120825 | Semiconductor device and method | Dec 13, 2020 | Issued |
Array
(
[id] => 16724058
[patent_doc_number] => 20210091205
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => MANUFACTURING METHOD OF AN HEMT TRANSISTOR OF THE NORMALLY OFF TYPE WITH REDUCED RESISTANCE IN THE ON STATE AND HEMT TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 17/118439
[patent_app_country] => US
[patent_app_date] => 2020-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4239
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118439
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/118439 | Manufacturing method of an HEMT transistor of the normally off type with reduced resistance in the on state and HEMT transistor | Dec 9, 2020 | Issued |
Array
(
[id] => 18211952
[patent_doc_number] => 20230058216
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-23
[patent_title] => A SELF-ALIGNING PREPARATION METHOD FOR A DRAIN END UNDERLAP REGION OF TUNNEL FIELD EFFECT TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 17/636980
[patent_app_country] => US
[patent_app_date] => 2020-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2163
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17636980
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/636980 | A SELF-ALIGNING PREPARATION METHOD FOR A DRAIN END UNDERLAP REGION OF TUNNEL FIELD EFFECT TRANSISTOR | Nov 29, 2020 | Abandoned |
Array
(
[id] => 16692359
[patent_doc_number] => 20210074838
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-11
[patent_title] => MANUFACTURING METHOD FOR FORMING INSULATING STRUCTURE OF HIGH ELECTRON MOBILITY TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 16/953286
[patent_app_country] => US
[patent_app_date] => 2020-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2979
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953286
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/953286 | Manufacturing method for forming insulating structure of high electron mobility transistor | Nov 18, 2020 | Issued |
Array
(
[id] => 16803442
[patent_doc_number] => 10998398
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-04
[patent_title] => Semiconductor device and method for manufacturing semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/952725
[patent_app_country] => US
[patent_app_date] => 2020-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 60
[patent_no_of_words] => 17181
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 412
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16952725
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/952725 | Semiconductor device and method for manufacturing semiconductor device | Nov 18, 2020 | Issued |
Array
(
[id] => 16660947
[patent_doc_number] => 20210057584
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-25
[patent_title] => TRANSISTOR AND SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/091218
[patent_app_country] => US
[patent_app_date] => 2020-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 24980
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17091218
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/091218 | Transistor and semiconductor device | Nov 5, 2020 | Issued |
Array
(
[id] => 16956182
[patent_doc_number] => 11060026
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-13
[patent_title] => Electronic device including quantum dots
[patent_app_type] => utility
[patent_app_number] => 17/083470
[patent_app_country] => US
[patent_app_date] => 2020-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 16665
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17083470
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/083470 | Electronic device including quantum dots | Oct 28, 2020 | Issued |
Array
(
[id] => 16624871
[patent_doc_number] => 20210043524
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-11
[patent_title] => METHOD FOR CALIBRATING TEMPERATURE IN CHEMICAL VAPOR DEPOSITION
[patent_app_type] => utility
[patent_app_number] => 17/080348
[patent_app_country] => US
[patent_app_date] => 2020-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5386
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080348
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/080348 | Method for calibrating temperature in chemical vapor deposition | Oct 25, 2020 | Issued |
Array
(
[id] => 17963976
[patent_doc_number] => 20220344557
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-27
[patent_title] => DISPLAY BACKPLANE AND FABRICATION METHOD THEREOF, DISPLAY PANEL AND FABRICATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/417660
[patent_app_country] => US
[patent_app_date] => 2020-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5086
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17417660
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/417660 | Display backplane and fabrication method thereof, display panel and fabrication method thereof | Oct 21, 2020 | Issued |
Array
(
[id] => 17638067
[patent_doc_number] => 11348800
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-31
[patent_title] => Ultra narrow trench patterning with dry plasma etching
[patent_app_type] => utility
[patent_app_number] => 17/073847
[patent_app_country] => US
[patent_app_date] => 2020-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 32
[patent_no_of_words] => 7795
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17073847
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/073847 | Ultra narrow trench patterning with dry plasma etching | Oct 18, 2020 | Issued |
Array
(
[id] => 18804459
[patent_doc_number] => 11837623
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-05
[patent_title] => Integrated circuit having vertical routing to bond pads
[patent_app_type] => utility
[patent_app_number] => 17/068223
[patent_app_country] => US
[patent_app_date] => 2020-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3083
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068223
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/068223 | Integrated circuit having vertical routing to bond pads | Oct 11, 2020 | Issued |
Array
(
[id] => 17925909
[patent_doc_number] => 11469172
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-11
[patent_title] => Semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 17/060851
[patent_app_country] => US
[patent_app_date] => 2020-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 21
[patent_no_of_words] => 10418
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17060851
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/060851 | Semiconductor devices | Sep 30, 2020 | Issued |
Array
(
[id] => 18447095
[patent_doc_number] => 11682671
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-20
[patent_title] => Integrated circuit structure and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/037447
[patent_app_country] => US
[patent_app_date] => 2020-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 5383
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037447
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/037447 | Integrated circuit structure and method for manufacturing the same | Sep 28, 2020 | Issued |
Array
(
[id] => 18145149
[patent_doc_number] => 20230019004
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 17/762206
[patent_app_country] => US
[patent_app_date] => 2020-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3074
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17762206
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/762206 | Lateral double-diffused metal oxide semiconductor field effect transistor | Sep 24, 2020 | Issued |
Array
(
[id] => 17486255
[patent_doc_number] => 20220093759
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-24
[patent_title] => SEMICONDUCTOR STRUCTURE HAVING BURIED GATE ELECTRODE WITH PROTRUDING MEMBER AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/030982
[patent_app_country] => US
[patent_app_date] => 2020-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7579
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030982
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/030982 | Semiconductor structure having buried gate electrode with protruding member and method of manufacturing the same | Sep 23, 2020 | Issued |
Array
(
[id] => 16865800
[patent_doc_number] => 11024553
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-01
[patent_title] => Semiconductor structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/031870
[patent_app_country] => US
[patent_app_date] => 2020-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7441
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031870
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/031870 | Semiconductor structure and manufacturing method thereof | Sep 23, 2020 | Issued |