
Phillips Iii
Examiner (ID: 1023, Phone: III ALBERT M )
| Most Active Art Unit | 2159 |
| Art Unit(s) | 2154, 2155, 2169, 2159 |
| Total Applications | 771 |
| Issued Applications | 616 |
| Pending Applications | 43 |
| Abandoned Applications | 127 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10697019
[patent_doc_number] => 20160043166
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-11
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/919084
[patent_app_country] => US
[patent_app_date] => 2015-10-21
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14919084
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/919084 | Semiconductor device and method of manufacturing the same | Oct 20, 2015 | Issued |
Array
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[patent_doc_number] => 20160035712
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-04
[patent_title] => 'MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/883977
[patent_app_country] => US
[patent_app_date] => 2015-10-15
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/883977 | Microelectronic package with stacked microelectronic units and method for manufacture thereof | Oct 14, 2015 | Issued |
Array
(
[id] => 11144117
[patent_doc_number] => 09379197
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-06-28
[patent_title] => 'Recess array device'
[patent_app_type] => utility
[patent_app_number] => 14/877889
[patent_app_country] => US
[patent_app_date] => 2015-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/877889 | Recess array device | Oct 6, 2015 | Issued |
Array
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[patent_doc_number] => 20170069730
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[patent_kind] => A1
[patent_issue_date] => 2017-03-09
[patent_title] => 'SEMICONDUCTOR PROCESS, PLANAR FIELD EFFECT TRANSISTOR AND FIN-SHAPED FIELD EFFECT TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 14/877926
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[patent_app_date] => 2015-10-07
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/877926 | Semiconductor process, planar field effect transistor and fin-shaped field effect transistor | Oct 6, 2015 | Issued |
Array
(
[id] => 11453419
[patent_doc_number] => 09577071
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[patent_issue_date] => 2017-02-21
[patent_title] => 'Method of making a strained structure of a semiconductor device'
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[patent_app_date] => 2015-10-06
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/875923 | Method of making a strained structure of a semiconductor device | Oct 5, 2015 | Issued |
Array
(
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[patent_doc_number] => 09899303
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[patent_kind] => B2
[patent_issue_date] => 2018-02-20
[patent_title] => 'Electronic package and fabrication method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/862457 | Electronic package and fabrication method thereof | Sep 22, 2015 | Issued |
Array
(
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[patent_doc_number] => 20170084537
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[patent_kind] => A1
[patent_issue_date] => 2017-03-23
[patent_title] => 'DUAL METAL-INSULATOR-SEMICONDUCTOR CONTACT STRUCTURE AND FORMULATION METHOD'
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[patent_app_number] => 14/862894
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/862894 | Dual metal-insulator-semiconductor contact structure and formulation method | Sep 22, 2015 | Issued |
Array
(
[id] => 11360314
[patent_doc_number] => 09536972
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-01-03
[patent_title] => 'Trench power MOSFET and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 14/862754
[patent_app_country] => US
[patent_app_date] => 2015-09-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/862754 | Trench power MOSFET and manufacturing method thereof | Sep 22, 2015 | Issued |
Array
(
[id] => 11753445
[patent_doc_number] => 09711464
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-18
[patent_title] => 'Semiconductor chip with anti-reverse engineering function'
[patent_app_type] => utility
[patent_app_number] => 14/862700
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/862700 | Semiconductor chip with anti-reverse engineering function | Sep 22, 2015 | Issued |
Array
(
[id] => 11517466
[patent_doc_number] => 20170084540
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[patent_kind] => A1
[patent_issue_date] => 2017-03-23
[patent_title] => 'Low-Temperature Diffusion Doping of Copper Interconnects Independent of Seed Layer Composition'
[patent_app_type] => utility
[patent_app_number] => 14/862580
[patent_app_country] => US
[patent_app_date] => 2015-09-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/862580 | Low-temperature diffusion doping of copper interconnects independent of seed layer composition | Sep 22, 2015 | Issued |
Array
(
[id] => 12666646
[patent_doc_number] => 20180114048
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[patent_kind] => A1
[patent_issue_date] => 2018-04-26
[patent_title] => CHIP PACKAGING METHOD AND CHIP PACKAGING STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 15/572455
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/572455 | CHIP PACKAGING METHOD AND CHIP PACKAGING STRUCTURE | Sep 15, 2015 | Abandoned |
Array
(
[id] => 13146295
[patent_doc_number] => 10090489
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[patent_issue_date] => 2018-10-02
[patent_title] => Organic electroluminescence apparatus, manufacturing method for same, illumination apparatus, and display apparatus
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Array
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[patent_issue_date] => 2017-01-31
[patent_title] => 'Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/829851 | Structure and method for interconnection | Aug 18, 2015 | Issued |
Array
(
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[patent_issue_date] => 2017-02-23
[patent_title] => 'ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR HIGH VOLTAGE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/829898 | Electrostatic discharge protection device for high voltage | Aug 18, 2015 | Issued |
Array
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[patent_title] => 'Forming CMOSFET structures with different contact liners'
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Array
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Array
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[patent_title] => 'METHOD FOR MANUFACTURING THIN FILM TRANSISTOR AND RELATED ACTIVE LAYER FOR THIN FILM TRANSISTOR, THIN FILM TRANSISTOR, ARRAY SUBSTRATE, AND DISPLAY APPARATUS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/822224 | Semiconductor device and method for manufacturing the same | Aug 9, 2015 | Issued |