Search

Phillips Iii

Examiner (ID: 1023, Phone: III ALBERT M )

Most Active Art Unit
2159
Art Unit(s)
2154, 2155, 2169, 2159
Total Applications
771
Issued Applications
616
Pending Applications
43
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10697019 [patent_doc_number] => 20160043166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/919084 [patent_app_country] => US [patent_app_date] => 2015-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6393 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14919084 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/919084
Semiconductor device and method of manufacturing the same Oct 20, 2015 Issued
Array ( [id] => 10689566 [patent_doc_number] => 20160035712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 14/883977 [patent_app_country] => US [patent_app_date] => 2015-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6284 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14883977 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/883977
Microelectronic package with stacked microelectronic units and method for manufacture thereof Oct 14, 2015 Issued
Array ( [id] => 11144117 [patent_doc_number] => 09379197 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-28 [patent_title] => 'Recess array device' [patent_app_type] => utility [patent_app_number] => 14/877889 [patent_app_country] => US [patent_app_date] => 2015-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1832 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14877889 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/877889
Recess array device Oct 6, 2015 Issued
Array ( [id] => 11495545 [patent_doc_number] => 20170069730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'SEMICONDUCTOR PROCESS, PLANAR FIELD EFFECT TRANSISTOR AND FIN-SHAPED FIELD EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/877926 [patent_app_country] => US [patent_app_date] => 2015-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14877926 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/877926
Semiconductor process, planar field effect transistor and fin-shaped field effect transistor Oct 6, 2015 Issued
Array ( [id] => 11453419 [patent_doc_number] => 09577071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Method of making a strained structure of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/875923 [patent_app_country] => US [patent_app_date] => 2015-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14875923 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/875923
Method of making a strained structure of a semiconductor device Oct 5, 2015 Issued
Array ( [id] => 12195567 [patent_doc_number] => 09899303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Electronic package and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 14/862457 [patent_app_country] => US [patent_app_date] => 2015-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 3374 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862457 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/862457
Electronic package and fabrication method thereof Sep 22, 2015 Issued
Array ( [id] => 11517463 [patent_doc_number] => 20170084537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'DUAL METAL-INSULATOR-SEMICONDUCTOR CONTACT STRUCTURE AND FORMULATION METHOD' [patent_app_type] => utility [patent_app_number] => 14/862894 [patent_app_country] => US [patent_app_date] => 2015-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5178 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862894 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/862894
Dual metal-insulator-semiconductor contact structure and formulation method Sep 22, 2015 Issued
Array ( [id] => 11360314 [patent_doc_number] => 09536972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Trench power MOSFET and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/862754 [patent_app_country] => US [patent_app_date] => 2015-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 7708 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862754 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/862754
Trench power MOSFET and manufacturing method thereof Sep 22, 2015 Issued
Array ( [id] => 11753445 [patent_doc_number] => 09711464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Semiconductor chip with anti-reverse engineering function' [patent_app_type] => utility [patent_app_number] => 14/862700 [patent_app_country] => US [patent_app_date] => 2015-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4328 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862700 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/862700
Semiconductor chip with anti-reverse engineering function Sep 22, 2015 Issued
Array ( [id] => 11517466 [patent_doc_number] => 20170084540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'Low-Temperature Diffusion Doping of Copper Interconnects Independent of Seed Layer Composition' [patent_app_type] => utility [patent_app_number] => 14/862580 [patent_app_country] => US [patent_app_date] => 2015-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862580 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/862580
Low-temperature diffusion doping of copper interconnects independent of seed layer composition Sep 22, 2015 Issued
Array ( [id] => 12666646 [patent_doc_number] => 20180114048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => CHIP PACKAGING METHOD AND CHIP PACKAGING STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/572455 [patent_app_country] => US [patent_app_date] => 2015-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15572455 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/572455
CHIP PACKAGING METHOD AND CHIP PACKAGING STRUCTURE Sep 15, 2015 Abandoned
Array ( [id] => 13146295 [patent_doc_number] => 10090489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Organic electroluminescence apparatus, manufacturing method for same, illumination apparatus, and display apparatus [patent_app_type] => utility [patent_app_number] => 15/506285 [patent_app_country] => US [patent_app_date] => 2015-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 13476 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15506285 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/506285
Organic electroluminescence apparatus, manufacturing method for same, illumination apparatus, and display apparatus Aug 19, 2015 Issued
Array ( [id] => 11411638 [patent_doc_number] => 09558950 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-31 [patent_title] => 'Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy' [patent_app_type] => utility [patent_app_number] => 14/829856 [patent_app_country] => US [patent_app_date] => 2015-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3405 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14829856 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/829856
Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy Aug 18, 2015 Issued
Array ( [id] => 11725235 [patent_doc_number] => 09698100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Structure and method for interconnection' [patent_app_type] => utility [patent_app_number] => 14/829851 [patent_app_country] => US [patent_app_date] => 2015-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 6270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14829851 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/829851
Structure and method for interconnection Aug 18, 2015 Issued
Array ( [id] => 11459999 [patent_doc_number] => 20170053905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR HIGH VOLTAGE' [patent_app_type] => utility [patent_app_number] => 14/829898 [patent_app_country] => US [patent_app_date] => 2015-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4813 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14829898 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/829898
Electrostatic discharge protection device for high voltage Aug 18, 2015 Issued
Array ( [id] => 11321615 [patent_doc_number] => 09520363 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-13 [patent_title] => 'Forming CMOSFET structures with different contact liners' [patent_app_type] => utility [patent_app_number] => 14/829850 [patent_app_country] => US [patent_app_date] => 2015-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4742 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14829850 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/829850
Forming CMOSFET structures with different contact liners Aug 18, 2015 Issued
Array ( [id] => 10472448 [patent_doc_number] => 20150357464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/826884 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6879 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14826884 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/826884
Semiconductor device Aug 13, 2015 Issued
Array ( [id] => 11367133 [patent_doc_number] => 20170005115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'METHOD FOR MANUFACTURING THIN FILM TRANSISTOR AND RELATED ACTIVE LAYER FOR THIN FILM TRANSISTOR, THIN FILM TRANSISTOR, ARRAY SUBSTRATE, AND DISPLAY APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/125786 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5373 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15125786 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/125786
Method for manufacturing thin film transistor and related active layer for thin film transistor, thin film transistor, array substrate, and display apparatus Aug 13, 2015 Issued
Array ( [id] => 11781779 [patent_doc_number] => 09390978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Method for producing semiconductor device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/823138 [patent_app_country] => US [patent_app_date] => 2015-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 141 [patent_no_of_words] => 9206 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14823138 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/823138
Method for producing semiconductor device and semiconductor device Aug 10, 2015 Issued
Array ( [id] => 10463826 [patent_doc_number] => 20150348841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/822224 [patent_app_country] => US [patent_app_date] => 2015-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2814 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14822224 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/822224
Semiconductor device and method for manufacturing the same Aug 9, 2015 Issued
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