
Phillips Iii
Examiner (ID: 1023, Phone: III ALBERT M )
| Most Active Art Unit | 2159 |
| Art Unit(s) | 2154, 2155, 2169, 2159 |
| Total Applications | 771 |
| Issued Applications | 616 |
| Pending Applications | 43 |
| Abandoned Applications | 127 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11681277
[patent_doc_number] => 09679811
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-13
[patent_title] => 'Semiconductor device and method of confining conductive bump material with solder mask patch'
[patent_app_type] => utility
[patent_app_number] => 14/144906
[patent_app_country] => US
[patent_app_date] => 2013-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 50
[patent_no_of_words] => 11958
[patent_no_of_claims] => 25
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14144906
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/144906 | Semiconductor device and method of confining conductive bump material with solder mask patch | Dec 30, 2013 | Issued |
Array
(
[id] => 10638423
[patent_doc_number] => 09355933
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-31
[patent_title] => 'Cooling channels in 3DIC stacks'
[patent_app_type] => utility
[patent_app_number] => 14/132515
[patent_app_country] => US
[patent_app_date] => 2013-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[patent_no_of_words] => 3407
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/132515 | Cooling channels in 3DIC stacks | Dec 17, 2013 | Issued |
Array
(
[id] => 10079837
[patent_doc_number] => 09117690
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-25
[patent_title] => 'Method for producing semiconductor device and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/083060
[patent_app_country] => US
[patent_app_date] => 2013-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 47
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[patent_no_of_words] => 9050
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14083060
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/083060 | Method for producing semiconductor device and semiconductor device | Nov 17, 2013 | Issued |
Array
(
[id] => 9995763
[patent_doc_number] => 09040357
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-05-26
[patent_title] => 'Semiconductor packaging method using connecting plate for internal connection'
[patent_app_type] => utility
[patent_app_number] => 14/083277
[patent_app_country] => US
[patent_app_date] => 2013-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14083277
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/083277 | Semiconductor packaging method using connecting plate for internal connection | Nov 17, 2013 | Issued |
Array
(
[id] => 10100175
[patent_doc_number] => 09136496
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-15
[patent_title] => 'Organic el device'
[patent_app_type] => utility
[patent_app_number] => 14/396134
[patent_app_country] => US
[patent_app_date] => 2013-11-13
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14396134
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/396134 | Organic el device | Nov 12, 2013 | Issued |
Array
(
[id] => 9363216
[patent_doc_number] => 20140073089
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-13
[patent_title] => 'CHIP PACKAGE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/077877
[patent_app_country] => US
[patent_app_date] => 2013-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/077877 | Chip package and manufacturing method thereof | Nov 11, 2013 | Issued |
Array
(
[id] => 9327881
[patent_doc_number] => 20140054663
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-27
[patent_title] => 'SOLID-STATE IMAGE SENSOR AND IMAGING SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 14/067817
[patent_app_country] => US
[patent_app_date] => 2013-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14067817
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/067817 | Solid-state image sensor and imaging system | Oct 29, 2013 | Issued |
Array
(
[id] => 9306646
[patent_doc_number] => 20140045320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-13
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/059873
[patent_app_country] => US
[patent_app_date] => 2013-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14059873
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/059873 | Semiconductor integrated circuit device and process for manufacturing the same | Oct 21, 2013 | Issued |
Array
(
[id] => 9306628
[patent_doc_number] => 20140045302
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-13
[patent_title] => 'Manufacturing Method of Submount'
[patent_app_type] => utility
[patent_app_number] => 14/058321
[patent_app_country] => US
[patent_app_date] => 2013-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14058321
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/058321 | Manufacturing Method of Submount | Oct 20, 2013 | Abandoned |
Array
(
[id] => 11796760
[patent_doc_number] => 09406607
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-08-02
[patent_title] => 'Device-manufacturing scheme for increasing the density of metal patterns in inter-layer dielectrics'
[patent_app_type] => utility
[patent_app_number] => 14/059123
[patent_app_country] => US
[patent_app_date] => 2013-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3418
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14059123
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/059123 | Device-manufacturing scheme for increasing the density of metal patterns in inter-layer dielectrics | Oct 20, 2013 | Issued |
Array
(
[id] => 9303952
[patent_doc_number] => 20140042626
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-13
[patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/059124
[patent_app_country] => US
[patent_app_date] => 2013-10-21
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14059124
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/059124 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE | Oct 20, 2013 | Abandoned |
Array
(
[id] => 10472177
[patent_doc_number] => 20150357193
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-10
[patent_title] => 'METHOD FOR PRODUCING AN EPITAXIAL SEMICONDUCTOR LAYER'
[patent_app_type] => utility
[patent_app_number] => 14/760601
[patent_app_country] => US
[patent_app_date] => 2013-10-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/760601 | METHOD FOR PRODUCING AN EPITAXIAL SEMICONDUCTOR LAYER | Oct 16, 2013 | Abandoned |
Array
(
[id] => 9958627
[patent_doc_number] => 09006838
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-14
[patent_title] => 'High sheet resistor in CMOS flow'
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[patent_app_number] => 14/050935
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[patent_app_date] => 2013-10-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/050935 | High sheet resistor in CMOS flow | Oct 9, 2013 | Issued |
Array
(
[id] => 9280893
[patent_doc_number] => 20140030861
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-30
[patent_title] => 'STRESS ENHANCED LDMOS TRANSISTOR TO MINIMIZE ON-RESISTANCE AND MAINTAIN HIGH BREAKDOWN VOLTAGE'
[patent_app_type] => utility
[patent_app_number] => 14/044163
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[patent_app_date] => 2013-10-02
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14044163
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/044163 | Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage | Oct 1, 2013 | Issued |
Array
(
[id] => 9294776
[patent_doc_number] => 20140038409
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-06
[patent_title] => 'SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/042938 | Semiconductor device and a method of manufacturing the same | Sep 30, 2013 | Issued |
Array
(
[id] => 11776325
[patent_doc_number] => 09385283
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-07-05
[patent_title] => 'Light emitting device equipped with protective member'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/036505 | Light emitting device equipped with protective member | Sep 24, 2013 | Issued |
Array
(
[id] => 10112254
[patent_doc_number] => 09147673
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-29
[patent_title] => 'Semiconductor power converter and method of manufacturing the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/025019 | Semiconductor power converter and method of manufacturing the same | Sep 11, 2013 | Issued |
Array
(
[id] => 9380856
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[patent_title] => 'SEMICONDUCTOR DEVICE'
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Array
(
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Array
(
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[patent_title] => 'INTERCONNECTION STRUCTURES AND FABRICATION METHOD THEREOF'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/020795 | Interconnection structures and fabrication method thereof | Sep 6, 2013 | Issued |