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Irina Kalish

Examiner (ID: 10416)

Most Active Art Unit
1714
Art Unit(s)
1714
Total Applications
6
Issued Applications
3
Pending Applications
0
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18788234 [patent_doc_number] => 20230376665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SYSTEMS AND METHODS FOR EXECUTING A PROGRAMMABLE FINITE STATE MACHINE THAT ACCELERATES FETCHLESS COMPUTATIONS AND OPERATIONS OF AN ARRAY OF PROCESSING CORES OF AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/230405 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230405 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230405
SYSTEMS AND METHODS FOR EXECUTING A PROGRAMMABLE FINITE STATE MACHINE THAT ACCELERATES FETCHLESS COMPUTATIONS AND OPERATIONS OF AN ARRAY OF PROCESSING CORES OF AN INTEGRATED CIRCUIT Aug 3, 2023 Pending
Array ( [id] => 18728242 [patent_doc_number] => 20230342535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => INTEGRATED CIRCUIT, SYSTEM AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/333259 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333259 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333259
INTEGRATED CIRCUIT, SYSTEM AND METHOD OF FORMING THE SAME Jun 11, 2023 Pending
Array ( [id] => 18897492 [patent_doc_number] => 20240012977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => ROUTING STRUCTURE AND METHOD OF WAFER SUBSTRATE WITH STANDARD INTEGRATION ZONE FOR INTEGRATION ON-WAFER [patent_app_type] => utility [patent_app_number] => 18/328800 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328800 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328800
ROUTING STRUCTURE AND METHOD OF WAFER SUBSTRATE WITH STANDARD INTEGRATION ZONE FOR INTEGRATION ON-WAFER Jun 4, 2023 Pending
Array ( [id] => 18651923 [patent_doc_number] => 20230297759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => INTEGRATED CIRCUIT STACK VERIFICATION METHOD AND SYSTEM FOR PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/323593 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323593 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323593
INTEGRATED CIRCUIT STACK VERIFICATION METHOD AND SYSTEM FOR PERFORMING THE SAME May 24, 2023 Pending
Array ( [id] => 18811162 [patent_doc_number] => 20230385498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => FAULT DIAGNOSTICS [patent_app_type] => utility [patent_app_number] => 18/303219 [patent_app_country] => US [patent_app_date] => 2023-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18303219 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/303219
FAULT DIAGNOSTICS Apr 18, 2023 Pending
Array ( [id] => 18470807 [patent_doc_number] => 20230205093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => METHOD OF MANUFACTURING PHOTO MASKS [patent_app_type] => utility [patent_app_number] => 18/114845 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18114845 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/114845
METHOD OF MANUFACTURING PHOTO MASKS Feb 26, 2023 Pending
Array ( [id] => 18258067 [patent_doc_number] => 20230085107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => VERIFYING A HARDWARE DESIGN FOR A MULTI-STAGE COMPONENT [patent_app_type] => utility [patent_app_number] => 17/990518 [patent_app_country] => US [patent_app_date] => 2022-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17990518 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/990518
VERIFYING A HARDWARE DESIGN FOR A MULTI-STAGE COMPONENT Nov 17, 2022 Pending
Array ( [id] => 18182030 [patent_doc_number] => 20230042759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => SEPARATION OF CONTRIBUTIONS TO METROLOGY DATA [patent_app_type] => utility [patent_app_number] => 17/968352 [patent_app_country] => US [patent_app_date] => 2022-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17968352 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/968352
SEPARATION OF CONTRIBUTIONS TO METROLOGY DATA Oct 17, 2022 Pending
Array ( [id] => 18209268 [patent_doc_number] => 20230055528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => SYSTEMS AND METHODS FOR EXECUTING A PROGRAMMABLE FINITE STATE MACHINE THAT ACCELERATES FETCHLESS COMPUTATIONS AND OPERATIONS OF AN ARRAY OF PROCESSING CORES OF AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/953312 [patent_app_country] => US [patent_app_date] => 2022-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953312 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/953312
Systems and methods for executing a programmable finite state machine that accelerates fetchless computations and operations of an array of processing cores of an integrated circuit Sep 25, 2022 Issued
Array ( [id] => 17839823 [patent_doc_number] => 20220277128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => Integrated Circuit Layouts with Fill Feature Shapes [patent_app_type] => utility [patent_app_number] => 17/745224 [patent_app_country] => US [patent_app_date] => 2022-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745224 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/745224
Integrated Circuit Layouts with Fill Feature Shapes May 15, 2022 Pending
Array ( [id] => 17932145 [patent_doc_number] => 20220327270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => METHOD, SYSTEM, MEDIUM, AND PROGRAM PRODUCT FOR PATH VERIFICATION IN LOGIC CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/709186 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4953 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/709186
METHOD, SYSTEM, MEDIUM, AND PROGRAM PRODUCT FOR PATH VERIFICATION IN LOGIC CIRCUIT Mar 29, 2022 Pending
Array ( [id] => 18651912 [patent_doc_number] => 20230297748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => HIERARCHICAL FLOOR-PLANNING FOR RAPID FPGA PROTOTYPING [patent_app_type] => utility [patent_app_number] => 17/695093 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695093
HIERARCHICAL FLOOR-PLANNING FOR RAPID FPGA PROTOTYPING Mar 14, 2022 Pending
Array ( [id] => 17885211 [patent_doc_number] => 20220300688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => FAST SYNTHESIS OF LOGICAL CIRCUIT DESIGN WITH PREDICTIVE TIMING [patent_app_type] => utility [patent_app_number] => 17/693236 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693236 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/693236
FAST SYNTHESIS OF LOGICAL CIRCUIT DESIGN WITH PREDICTIVE TIMING Mar 10, 2022 Pending
Array ( [id] => 18487221 [patent_doc_number] => 20230214567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => METHOD FOR OPTIMIZING CIRCUIT TIMING BASED ON FLEXIBLE REGISTER TIMING LIBRARY [patent_app_type] => utility [patent_app_number] => 18/011443 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 730 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18011443 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/011443
Method for optimizing circuit timing based on flexible register timing library Mar 8, 2022 Issued
Array ( [id] => 18454705 [patent_doc_number] => 20230195985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => FLEXIBLE MODELING METHOD FOR TIMING CONSTRAINT OF REGISTER [patent_app_type] => utility [patent_app_number] => 18/014002 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18014002 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/014002
Flexible modeling method for timing constraint of register Mar 8, 2022 Issued
Array ( [id] => 17629502 [patent_doc_number] => 20220164517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => FAILSAFE CIRCUIT, LAYOUT, DEVICE, AND METHOD [patent_app_type] => utility [patent_app_number] => 17/667478 [patent_app_country] => US [patent_app_date] => 2022-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17667478 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/667478
FAILSAFE CIRCUIT, LAYOUT, DEVICE, AND METHOD Feb 7, 2022 Pending
Array ( [id] => 18165994 [patent_doc_number] => 20230032595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => AUTOMATED REDISTRIBUTION LAYER POWER CONNECTIONS [patent_app_type] => utility [patent_app_number] => 17/564725 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564725 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564725
AUTOMATED REDISTRIBUTION LAYER POWER CONNECTIONS Dec 28, 2021 Pending
Array ( [id] => 18163168 [patent_doc_number] => 20230029761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => Run-time reconfigurable accelerator for matrix multiplication [patent_app_type] => utility [patent_app_number] => 17/552289 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552289 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/552289
Run-time reconfigurable accelerator for matrix multiplication Dec 14, 2021 Pending
Array ( [id] => 18439685 [patent_doc_number] => 20230186980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SYNTHESIZABLE LOGIC MEMORY [patent_app_type] => utility [patent_app_number] => 17/546408 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546408 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546408
SYNTHESIZABLE LOGIC MEMORY Dec 8, 2021 Pending
Array ( [id] => 18366827 [patent_doc_number] => 20230148419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => DYNAMIC PORT HANDLING FOR ISOLATED MODULES AND DYNAMIC FUNCTION EXCHANGE [patent_app_type] => utility [patent_app_number] => 17/522834 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522834 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522834
DYNAMIC PORT HANDLING FOR ISOLATED MODULES AND DYNAMIC FUNCTION EXCHANGE Nov 8, 2021 Pending
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