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Irina Kalish

Examiner (ID: 10416)

Most Active Art Unit
1714
Art Unit(s)
1714
Total Applications
6
Issued Applications
3
Pending Applications
0
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15059529 [patent_doc_number] => 10460071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Shaped beam lithography including temperature effects [patent_app_type] => utility [patent_app_number] => 15/298464 [patent_app_country] => US [patent_app_date] => 2016-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 14241 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15298464 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/298464
Shaped beam lithography including temperature effects Oct 19, 2016 Issued
Array ( [id] => 11990276 [patent_doc_number] => 20170294430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'STANDARD CELL FOR REMOVING ROUTING INTERFERENCE BETWEEN ADJACENT PINS AND DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/298586 [patent_app_country] => US [patent_app_date] => 2016-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10638 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15298586 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/298586
Standard cell for removing routing interference between adjacent pins and device including the same Oct 19, 2016 Issued
Array ( [id] => 11570826 [patent_doc_number] => 20170109470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'LOGIC YIELD LEARNING VEHICLE WITH PHASED DESIGN WINDOWS' [patent_app_type] => utility [patent_app_number] => 15/298123 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4926 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15298123 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/298123
Logic yield learning vehicle with phased design windows Oct 18, 2016 Issued
Array ( [id] => 11494568 [patent_doc_number] => 20170068753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'Self Equivalence in Hardware Designs' [patent_app_type] => utility [patent_app_number] => 15/256185 [patent_app_country] => US [patent_app_date] => 2016-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4058 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15256185 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/256185
Self Equivalence in Hardware Designs Sep 1, 2016 Abandoned
Array ( [id] => 16033123 [patent_doc_number] => 10678985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Method for generating three-dimensional integrated circuit design [patent_app_type] => utility [patent_app_number] => 15/252592 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7544 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 400 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15252592 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/252592
Method for generating three-dimensional integrated circuit design Aug 30, 2016 Issued
Array ( [id] => 11966080 [patent_doc_number] => 20170270234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'CIRCUIT DESIGN VERIFICATION APPARATUS AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 15/253517 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15253517 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/253517
Circuit design verification apparatus and program Aug 30, 2016 Issued
Array ( [id] => 11556908 [patent_doc_number] => 20170103154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'CIRCUIT DESIGN METHOD AND SIMULATION METHOD BASED ON PROCESS VARIATION CAUSED BY AGING' [patent_app_type] => utility [patent_app_number] => 15/251411 [patent_app_country] => US [patent_app_date] => 2016-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9748 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15251411 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/251411
CIRCUIT DESIGN METHOD AND SIMULATION METHOD BASED ON PROCESS VARIATION CAUSED BY AGING Aug 29, 2016 Abandoned
Array ( [id] => 11474274 [patent_doc_number] => 20170061057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'INTEGRATED CIRCUIT DESIGN METHOD REDUCING CLOCK POWER AND INTEGRATED CLOCK GATER MERGED WITH FLIP-FLOPS' [patent_app_type] => utility [patent_app_number] => 15/249611 [patent_app_country] => US [patent_app_date] => 2016-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15249611 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/249611
INTEGRATED CIRCUIT DESIGN METHOD REDUCING CLOCK POWER AND INTEGRATED CLOCK GATER MERGED WITH FLIP-FLOPS Aug 28, 2016 Abandoned
Array ( [id] => 14299273 [patent_doc_number] => 10289764 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-14 [patent_title] => Parallel extraction of worst case corners [patent_app_type] => utility [patent_app_number] => 15/247675 [patent_app_country] => US [patent_app_date] => 2016-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7744 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15247675 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/247675
Parallel extraction of worst case corners Aug 24, 2016 Issued
Array ( [id] => 14458157 [patent_doc_number] => 10325042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-18 [patent_title] => Debugging failures in X-propagation logic circuit simulation [patent_app_type] => utility [patent_app_number] => 15/247798 [patent_app_country] => US [patent_app_date] => 2016-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7477 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15247798 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/247798
Debugging failures in X-propagation logic circuit simulation Aug 24, 2016 Issued
Array ( [id] => 12222093 [patent_doc_number] => 20180060453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'UNIVERSAL VERIFICATION METHODOLOGY (UVM) REGISTER ABSTRACTION LAYER (RAL) PAINTER' [patent_app_type] => utility [patent_app_number] => 15/245404 [patent_app_country] => US [patent_app_date] => 2016-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7214 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15245404 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/245404
UNIVERSAL VERIFICATION METHODOLOGY (UVM) REGISTER ABSTRACTION LAYER (RAL) PAINTER Aug 23, 2016 Abandoned
Array ( [id] => 11272841 [patent_doc_number] => 20160335387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'Design Tools For Converting a FinFet Circuit into a Circuit Including Nanowires and 2D Material Strips' [patent_app_type] => utility [patent_app_number] => 15/222760 [patent_app_country] => US [patent_app_date] => 2016-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 22398 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15222760 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/222760
Design Tools For Converting a FinFet Circuit into a Circuit Including Nanowires and 2D Material Strips Jul 27, 2016 Abandoned
Array ( [id] => 11474284 [patent_doc_number] => 20170061067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'TIMING WINDOW MANIPULATION FOR NOISE REDUCTION' [patent_app_type] => utility [patent_app_number] => 15/213473 [patent_app_country] => US [patent_app_date] => 2016-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5685 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15213473 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/213473
TIMING WINDOW MANIPULATION FOR NOISE REDUCTION Jul 18, 2016 Abandoned
Array ( [id] => 11103035 [patent_doc_number] => 20160300005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'CELL LAYOUT UTILIZING BOUNDARY CELL WITH MIXED POLY PITCH WITHIN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/081936 [patent_app_country] => US [patent_app_date] => 2016-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15081936 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/081936
Cell layout utilizing boundary cell with mixed poly pitch within integrated circuit Mar 26, 2016 Issued
Array ( [id] => 14556237 [patent_doc_number] => 10346580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Checking wafer-level integrated designs for rule compliance [patent_app_type] => utility [patent_app_number] => 15/081226 [patent_app_country] => US [patent_app_date] => 2016-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5328 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15081226 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/081226
Checking wafer-level integrated designs for rule compliance Mar 24, 2016 Issued
Array ( [id] => 11086677 [patent_doc_number] => 20160283643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'SYSTEM AND METHOD OF ANALYZING INTEGRATED CIRCUIT IN CONSIDERATION OF A PROCESS VARIATION' [patent_app_type] => utility [patent_app_number] => 15/081291 [patent_app_country] => US [patent_app_date] => 2016-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 14990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15081291 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/081291
System and method of analyzing integrated circuit in consideration of a process variation Mar 24, 2016 Issued
Array ( [id] => 16146263 [patent_doc_number] => 10706203 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-07 [patent_title] => Method and apparatus for verifying initial state equivalence of changed registers in retimed circuits [patent_app_type] => utility [patent_app_number] => 15/079518 [patent_app_country] => US [patent_app_date] => 2016-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15804 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15079518 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/079518
Method and apparatus for verifying initial state equivalence of changed registers in retimed circuits Mar 23, 2016 Issued
Array ( [id] => 10816466 [patent_doc_number] => 20160162626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'LITHOGRAPHY PROCESS WINDOW PREDICTION BASED ON DESIGN DATA' [patent_app_type] => utility [patent_app_number] => 15/042779 [patent_app_country] => US [patent_app_date] => 2016-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8869 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15042779 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/042779
LITHOGRAPHY PROCESS WINDOW PREDICTION BASED ON DESIGN DATA Feb 11, 2016 Abandoned
Array ( [id] => 11839006 [patent_doc_number] => 20170220726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'METHOD AND SYSTEM FOR PERFORMING A DESIGN SPACE EXPLORATION OF A CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/010814 [patent_app_country] => US [patent_app_date] => 2016-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9870 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15010814 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/010814
METHOD AND SYSTEM FOR PERFORMING A DESIGN SPACE EXPLORATION OF A CIRCUIT Jan 28, 2016 Abandoned
Array ( [id] => 15059527 [patent_doc_number] => 10460070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Optimized electromigration analysis [patent_app_type] => utility [patent_app_number] => 15/008546 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15008546 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/008546
Optimized electromigration analysis Jan 27, 2016 Issued
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