Irina Kalish
Examiner (ID: 10416)
Most Active Art Unit | 1714 |
Art Unit(s) | 1714 |
Total Applications | 6 |
Issued Applications | 3 |
Pending Applications | 0 |
Abandoned Applications | 3 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
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[patent_doc_number] => 10460071
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[patent_issue_date] => 2019-10-29
[patent_title] => Shaped beam lithography including temperature effects
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[patent_issue_date] => 2017-10-12
[patent_title] => 'STANDARD CELL FOR REMOVING ROUTING INTERFERENCE BETWEEN ADJACENT PINS AND DEVICE INCLUDING THE SAME'
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Array
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[patent_issue_date] => 2017-04-20
[patent_title] => 'LOGIC YIELD LEARNING VEHICLE WITH PHASED DESIGN WINDOWS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/298123 | Logic yield learning vehicle with phased design windows | Oct 18, 2016 | Issued |
Array
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[patent_title] => 'Self Equivalence in Hardware Designs'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/252592 | Method for generating three-dimensional integrated circuit design | Aug 30, 2016 | Issued |
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Array
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[patent_doc_number] => 20170061057
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[patent_issue_date] => 2017-03-02
[patent_title] => 'INTEGRATED CIRCUIT DESIGN METHOD REDUCING CLOCK POWER AND INTEGRATED CLOCK GATER MERGED WITH FLIP-FLOPS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/249611 | INTEGRATED CIRCUIT DESIGN METHOD REDUCING CLOCK POWER AND INTEGRATED CLOCK GATER MERGED WITH FLIP-FLOPS | Aug 28, 2016 | Abandoned |
Array
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[id] => 14299273
[patent_doc_number] => 10289764
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[patent_issue_date] => 2019-05-14
[patent_title] => Parallel extraction of worst case corners
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/247675 | Parallel extraction of worst case corners | Aug 24, 2016 | Issued |
Array
(
[id] => 14458157
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[patent_title] => Debugging failures in X-propagation logic circuit simulation
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Array
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[id] => 12222093
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[patent_issue_date] => 2018-03-01
[patent_title] => 'UNIVERSAL VERIFICATION METHODOLOGY (UVM) REGISTER ABSTRACTION LAYER (RAL) PAINTER'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/245404 | UNIVERSAL VERIFICATION METHODOLOGY (UVM) REGISTER ABSTRACTION LAYER (RAL) PAINTER | Aug 23, 2016 | Abandoned |
Array
(
[id] => 11272841
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[patent_title] => 'Design Tools For Converting a FinFet Circuit into a Circuit Including Nanowires and 2D Material Strips'
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Array
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[id] => 11474284
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Array
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[id] => 11103035
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/081936 | Cell layout utilizing boundary cell with mixed poly pitch within integrated circuit | Mar 26, 2016 | Issued |
Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/008546 | Optimized electromigration analysis | Jan 27, 2016 | Issued |