Search

Irina Kalish

Examiner (ID: 10416)

Most Active Art Unit
1714
Art Unit(s)
1714
Total Applications
6
Issued Applications
3
Pending Applications
0
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15013305 [patent_doc_number] => 10452800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Routing of nets of an integrated circuit [patent_app_type] => utility [patent_app_number] => 14/741504 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7721 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 673 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14741504 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/741504
Routing of nets of an integrated circuit Jun 16, 2015 Issued
Array ( [id] => 11338760 [patent_doc_number] => 20160364515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'METHODS AND DEVICES FOR EXTRACTION OF MEMS STRUCTURES FROM A MEMS LAYOUT' [patent_app_type] => utility [patent_app_number] => 14/740075 [patent_app_country] => US [patent_app_date] => 2015-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 15938 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14740075 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/740075
Methods and devices for extraction of MEMS structures from a MEMS layout Jun 14, 2015 Issued
Array ( [id] => 13281955 [patent_doc_number] => 10152565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Methods for performing register retiming operations into synchronization regions interposed between circuits associated with different clock domains [patent_app_type] => utility [patent_app_number] => 14/730082 [patent_app_country] => US [patent_app_date] => 2015-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11316 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14730082 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/730082
Methods for performing register retiming operations into synchronization regions interposed between circuits associated with different clock domains Jun 2, 2015 Issued
Array ( [id] => 11327286 [patent_doc_number] => 20160357898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'DESIGN OF TEMPERATURE-COMPLIANT INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/728100 [patent_app_country] => US [patent_app_date] => 2015-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14728100 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/728100
Temperature-compliant integrated circuits Jun 1, 2015 Issued
Array ( [id] => 11314337 [patent_doc_number] => 20160350448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'STATE CHART ENHANCEMENT' [patent_app_type] => utility [patent_app_number] => 14/727544 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 10563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727544 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/727544
STATE CHART ENHANCEMENT May 31, 2015 Abandoned
Array ( [id] => 11314336 [patent_doc_number] => 20160350447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'GENERATING PATH EXECUTION TIMES' [patent_app_type] => utility [patent_app_number] => 14/727517 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727517 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/727517
GENERATING PATH EXECUTION TIMES May 31, 2015 Abandoned
Array ( [id] => 11314339 [patent_doc_number] => 20160350450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'COMBINATION MAP BASED COMPOSITE DESIGN' [patent_app_type] => utility [patent_app_number] => 14/727598 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9396 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727598 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/727598
COMBINATION MAP BASED COMPOSITE DESIGN May 31, 2015 Abandoned
Array ( [id] => 14705119 [patent_doc_number] => 10380309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Boolean logic optimization in majority-inverter graphs [patent_app_type] => utility [patent_app_number] => 14/727114 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5609 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727114 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/727114
Boolean logic optimization in majority-inverter graphs May 31, 2015 Issued
Array ( [id] => 14857275 [patent_doc_number] => 10417367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => System for placement optimization of chip design for transient noise control and related methods thereof [patent_app_type] => utility [patent_app_number] => 14/727277 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8769 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727277 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/727277
System for placement optimization of chip design for transient noise control and related methods thereof May 31, 2015 Issued
Array ( [id] => 11314338 [patent_doc_number] => 20160350449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'EXCEPTIONAL LOGIC ELEMENT MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 14/727580 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727580 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/727580
EXCEPTIONAL LOGIC ELEMENT MANAGEMENT May 31, 2015 Abandoned
Array ( [id] => 12797833 [patent_doc_number] => 20180157780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => DRIFT COMPENSATION [patent_app_type] => utility [patent_app_number] => 15/569931 [patent_app_country] => US [patent_app_date] => 2015-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15569931 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/569931
Drift compensation Apr 27, 2015 Issued
Array ( [id] => 14427773 [patent_doc_number] => 10318692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Scalable chip placement [patent_app_type] => utility [patent_app_number] => 14/665716 [patent_app_country] => US [patent_app_date] => 2015-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6364 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14665716 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/665716
Scalable chip placement Mar 22, 2015 Issued
Array ( [id] => 11078260 [patent_doc_number] => 20160275224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'APPARATUS AND METHOD FOR GENERATING A REDUCED NUMBER OF TEST VECTORS AND INSERTING TEST POINTS FOR A LOGIC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/664749 [patent_app_country] => US [patent_app_date] => 2015-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14664749 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/664749
APPARATUS AND METHOD FOR GENERATING A REDUCED NUMBER OF TEST VECTORS AND INSERTING TEST POINTS FOR A LOGIC CIRCUIT Mar 19, 2015 Abandoned
Array ( [id] => 12496095 [patent_doc_number] => 09996650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Modeling the performance of a field effect transistor having a dynamically depleted channel region [patent_app_type] => utility [patent_app_number] => 14/660334 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 14564 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 627 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14660334 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/660334
Modeling the performance of a field effect transistor having a dynamically depleted channel region Mar 16, 2015 Issued
Array ( [id] => 11078264 [patent_doc_number] => 20160275227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'OPTIMIZING INTERCONNECT DESIGNS IN LOW-POWER INTEGRATED CIRCUITS (ICs)' [patent_app_type] => utility [patent_app_number] => 14/658504 [patent_app_country] => US [patent_app_date] => 2015-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14658504 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/658504
OPTIMIZING INTERCONNECT DESIGNS IN LOW-POWER INTEGRATED CIRCUITS (ICs) Mar 15, 2015 Abandoned
Array ( [id] => 13120733 [patent_doc_number] => 10078720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-18 [patent_title] => Methods and systems for circuit fault diagnosis [patent_app_type] => utility [patent_app_number] => 14/656834 [patent_app_country] => US [patent_app_date] => 2015-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14656834 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/656834
Methods and systems for circuit fault diagnosis Mar 12, 2015 Issued
Array ( [id] => 10512324 [patent_doc_number] => 09239902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-19 [patent_title] => 'Method of preparing a layout and system for performing the same' [patent_app_type] => utility [patent_app_number] => 14/625959 [patent_app_country] => US [patent_app_date] => 2015-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14625959 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/625959
Method of preparing a layout and system for performing the same Feb 18, 2015 Issued
Array ( [id] => 11042643 [patent_doc_number] => 20160239599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'LAYOUT CHECKING METHOD FOR ADVANCED DOUBLE PATTERNING PHOTOLITHOGRAPHY WITH MULTIPLE SPACING CRITERIA' [patent_app_type] => utility [patent_app_number] => 14/622009 [patent_app_country] => US [patent_app_date] => 2015-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12719 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14622009 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/622009
Layout checking method for advanced double patterning photolithography with multiple spacing criteria Feb 12, 2015 Issued
Array ( [id] => 10349973 [patent_doc_number] => 20150234978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'Cell Internal Defect Diagnosis' [patent_app_type] => utility [patent_app_number] => 14/621868 [patent_app_country] => US [patent_app_date] => 2015-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14621868 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/621868
Cell Internal Defect Diagnosis Feb 12, 2015 Abandoned
Array ( [id] => 11042642 [patent_doc_number] => 20160239598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'INTEGRATED CIRCUIT STACK VERIFICATION METHOD AND SYSTEM FOR PERFORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/621054 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5449 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14621054 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/621054
Integrated circuit stack verification method and system for performing the same Feb 11, 2015 Issued
Menu