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Irina Kalish

Examiner (ID: 10416)

Most Active Art Unit
1714
Art Unit(s)
1714
Total Applications
6
Issued Applications
3
Pending Applications
0
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10384290 [patent_doc_number] => 20150269297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'METHODS FOR REDUCING POST LAYOUT CIRCUIT SIMULATION RESULTS' [patent_app_type] => utility [patent_app_number] => 14/219947 [patent_app_country] => US [patent_app_date] => 2014-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 12070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14219947 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/219947
METHODS FOR REDUCING POST LAYOUT CIRCUIT SIMULATION RESULTS Mar 18, 2014 Abandoned
Array ( [id] => 10384290 [patent_doc_number] => 20150269297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'METHODS FOR REDUCING POST LAYOUT CIRCUIT SIMULATION RESULTS' [patent_app_type] => utility [patent_app_number] => 14/219947 [patent_app_country] => US [patent_app_date] => 2014-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 12070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14219947 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/219947
METHODS FOR REDUCING POST LAYOUT CIRCUIT SIMULATION RESULTS Mar 18, 2014 Abandoned
Array ( [id] => 12955054 [patent_doc_number] => 09837845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Charging controlling circuit and charging controlling system [patent_app_type] => utility [patent_app_number] => 14/184052 [patent_app_country] => US [patent_app_date] => 2014-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5163 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 722 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14184052 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/184052
Charging controlling circuit and charging controlling system Feb 18, 2014 Issued
Array ( [id] => 9668470 [patent_doc_number] => 20140232333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'ADJUSTING OPERATION OF AN ELECTRONIC DEVICE IN RESPONSE TO A SUDDEN-POWER-OFF (SPO) EVENT' [patent_app_type] => utility [patent_app_number] => 14/183935 [patent_app_country] => US [patent_app_date] => 2014-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14183935 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/183935
ADJUSTING OPERATION OF AN ELECTRONIC DEVICE IN RESPONSE TO A SUDDEN-POWER-OFF (SPO) EVENT Feb 18, 2014 Abandoned
Array ( [id] => 9668469 [patent_doc_number] => 20140232332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'CHARGING CIRCUIT FOR AN ENERGY STORAGE DEVICE, AND METHOD FOR CHARGING AN ENERGY STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/183619 [patent_app_country] => US [patent_app_date] => 2014-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5985 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14183619 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/183619
CHARGING CIRCUIT FOR AN ENERGY STORAGE DEVICE, AND METHOD FOR CHARGING AN ENERGY STORAGE DEVICE Feb 18, 2014 Abandoned
Array ( [id] => 9683141 [patent_doc_number] => 20140239904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'COMPACT STRUCTURE OF BATTERY UNIT' [patent_app_type] => utility [patent_app_number] => 14/183694 [patent_app_country] => US [patent_app_date] => 2014-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11413 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14183694 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/183694
COMPACT STRUCTURE OF BATTERY UNIT Feb 18, 2014 Abandoned
Array ( [id] => 10349969 [patent_doc_number] => 20150234974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'MULTIPLE PATTERNING DESIGN WITH REDUCED COMPLEXITY' [patent_app_type] => utility [patent_app_number] => 14/181990 [patent_app_country] => US [patent_app_date] => 2014-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6659 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14181990 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/181990
MULTIPLE PATTERNING DESIGN WITH REDUCED COMPLEXITY Feb 16, 2014 Abandoned
Array ( [id] => 9834612 [patent_doc_number] => 08943446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-27 [patent_title] => 'Generation method, storage medium and information processing apparatus' [patent_app_type] => utility [patent_app_number] => 14/174083 [patent_app_country] => US [patent_app_date] => 2014-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 5415 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14174083 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/174083
Generation method, storage medium and information processing apparatus Feb 5, 2014 Issued
Array ( [id] => 11598955 [patent_doc_number] => 09646125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-09 [patent_title] => 'Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor' [patent_app_type] => utility [patent_app_number] => 14/151866 [patent_app_country] => US [patent_app_date] => 2014-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7920 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 409 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14151866 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/151866
Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor Jan 9, 2014 Issued
Array ( [id] => 9853158 [patent_doc_number] => 08954906 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-02-10 [patent_title] => 'Method and apparatus for performing parallel synthesis on a field programmable gate array' [patent_app_type] => utility [patent_app_number] => 14/152570 [patent_app_country] => US [patent_app_date] => 2014-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 7756 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14152570 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/152570
Method and apparatus for performing parallel synthesis on a field programmable gate array Jan 9, 2014 Issued
Array ( [id] => 10879520 [patent_doc_number] => 08904318 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-02 [patent_title] => 'Method and apparatus for performing optimization using don\'t care states' [patent_app_type] => utility [patent_app_number] => 14/150424 [patent_app_country] => US [patent_app_date] => 2014-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7667 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14150424 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/150424
Method and apparatus for performing optimization using don't care states Jan 7, 2014 Issued
Array ( [id] => 9999117 [patent_doc_number] => 09043734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-26 [patent_title] => 'Method and system for forming high accuracy patterns using charged particle beam lithography' [patent_app_type] => utility [patent_app_number] => 14/106584 [patent_app_country] => US [patent_app_date] => 2013-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 11489 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14106584 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/106584
Method and system for forming high accuracy patterns using charged particle beam lithography Dec 12, 2013 Issued
Array ( [id] => 9515758 [patent_doc_number] => 20140152250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'SYSTEM AND METHOD FOR CONTROLLING OUTPUT POWER IN A CONTACTLESS POWER TRANSFER SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/088955 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3719 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14088955 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/088955
SYSTEM AND METHOD FOR CONTROLLING OUTPUT POWER IN A CONTACTLESS POWER TRANSFER SYSTEM Nov 24, 2013 Abandoned
Array ( [id] => 11645691 [patent_doc_number] => 09667093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-30 [patent_title] => 'Transportable power plant apparatus and method' [patent_app_type] => utility [patent_app_number] => 14/088384 [patent_app_country] => US [patent_app_date] => 2013-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 4326 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14088384 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/088384
Transportable power plant apparatus and method Nov 22, 2013 Issued
Array ( [id] => 9800960 [patent_doc_number] => 20150012904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'SYSTEM AND METHOD FOR SETTING ELECTRICAL SPECIFICATION OF SIGNAL TRANSMISSION LINE' [patent_app_type] => utility [patent_app_number] => 14/086973 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 613 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14086973 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/086973
SYSTEM AND METHOD FOR SETTING ELECTRICAL SPECIFICATION OF SIGNAL TRANSMISSION LINE Nov 21, 2013 Abandoned
Array ( [id] => 14203359 [patent_doc_number] => 10268797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Architectural physical synthesis [patent_app_type] => utility [patent_app_number] => 14/086911 [patent_app_country] => US [patent_app_date] => 2013-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 12688 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14086911 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/086911
Architectural physical synthesis Nov 20, 2013 Issued
Array ( [id] => 10258308 [patent_doc_number] => 20150143305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'RETICLE DATA DECOMPOSITION FOR FOCAL PLANE DETERMINATION IN LITHOGRAPHIC PROCESSES' [patent_app_type] => utility [patent_app_number] => 14/083578 [patent_app_country] => US [patent_app_date] => 2013-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14083578 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/083578
Reticle data decomposition for focal plane determination in lithographic processes Nov 18, 2013 Issued
Array ( [id] => 12551913 [patent_doc_number] => 10013520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Method of determining if layout design is N-colorable [patent_app_type] => utility [patent_app_number] => 14/045532 [patent_app_country] => US [patent_app_date] => 2013-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 8726 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 454 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14045532 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/045532
Method of determining if layout design is N-colorable Oct 2, 2013 Issued
Array ( [id] => 10204469 [patent_doc_number] => 20150089457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'Hierarchical Approach to Triple Patterning Decomposition' [patent_app_type] => utility [patent_app_number] => 14/037587 [patent_app_country] => US [patent_app_date] => 2013-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5901 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14037587 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/037587
Hierarchical Approach to Triple Patterning Decomposition Sep 25, 2013 Abandoned
Array ( [id] => 9211947 [patent_doc_number] => 20140011124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING' [patent_app_type] => utility [patent_app_number] => 14/021711 [patent_app_country] => US [patent_app_date] => 2013-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7548 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14021711 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/021711
METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING Sep 8, 2013 Abandoned
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