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Irina Kalish

Examiner (ID: 10416)

Most Active Art Unit
1714
Art Unit(s)
1714
Total Applications
6
Issued Applications
3
Pending Applications
0
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9548900 [patent_doc_number] => 20140173548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'Tool For Automation Of Functional Safety Metric Calculation And Prototyping Of Functional Safety Systems' [patent_app_type] => utility [patent_app_number] => 14/020802 [patent_app_country] => US [patent_app_date] => 2013-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6436 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14020802 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/020802
Tool For Automation Of Functional Safety Metric Calculation And Prototyping Of Functional Safety Systems Sep 6, 2013 Abandoned
Array ( [id] => 9214111 [patent_doc_number] => 20140013288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'METHOD AND DEVICE FOR INCREASING FIN DEVICE DENSITY FOR UNALIGNED FINS' [patent_app_type] => utility [patent_app_number] => 14/018133 [patent_app_country] => US [patent_app_date] => 2013-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14018133 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/018133
Method and device for increasing fin device density for unaligned fins Sep 3, 2013 Issued
Array ( [id] => 9912424 [patent_doc_number] => 20150067627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'RAPID EXPRESSION COVERAGE' [patent_app_type] => utility [patent_app_number] => 14/013925 [patent_app_country] => US [patent_app_date] => 2013-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9259 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14013925 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/013925
Rapid expression coverage Aug 28, 2013 Issued
Array ( [id] => 9260907 [patent_doc_number] => 20130342836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'COMB-BASED SPECTROSCOPY WITH SYNCHRONOUS SAMPLING FOR REAL-TIME AVERAGING' [patent_app_type] => utility [patent_app_number] => 14/012436 [patent_app_country] => US [patent_app_date] => 2013-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14455 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14012436 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/012436
Comb-based spectroscopy with synchronous sampling for real-time averaging Aug 27, 2013 Issued
Array ( [id] => 9540375 [patent_doc_number] => 20140165022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'RELATIVE TIMING ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/945843 [patent_app_country] => US [patent_app_date] => 2013-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13805 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13945843 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/945843
RELATIVE TIMING ARCHITECTURE Jul 17, 2013 Abandoned
Array ( [id] => 9266989 [patent_doc_number] => 20140021905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-23 [patent_title] => 'USB CONVERTER ADAPTOR' [patent_app_type] => utility [patent_app_number] => 13/942971 [patent_app_country] => US [patent_app_date] => 2013-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1880 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13942971 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/942971
USB CONVERTER ADAPTOR Jul 15, 2013 Abandoned
Array ( [id] => 9683140 [patent_doc_number] => 20140239903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'POWER CONVERSION DEVICE HAVING BATTERY HEATING FUNCTION' [patent_app_type] => utility [patent_app_number] => 13/942952 [patent_app_country] => US [patent_app_date] => 2013-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4928 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13942952 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/942952
POWER CONVERSION DEVICE HAVING BATTERY HEATING FUNCTION Jul 15, 2013 Abandoned
Array ( [id] => 9267007 [patent_doc_number] => 20140021923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-23 [patent_title] => 'ELECTRICAL STORAGE SYSTEM, AND CONTROL METHOD FOR ELECTRICAL STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/943135 [patent_app_country] => US [patent_app_date] => 2013-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13115 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943135 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943135
ELECTRICAL STORAGE SYSTEM, AND CONTROL METHOD FOR ELECTRICAL STORAGE SYSTEM Jul 15, 2013 Abandoned
Array ( [id] => 10630203 [patent_doc_number] => 09348351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-24 [patent_title] => 'Switch circuit' [patent_app_type] => utility [patent_app_number] => 13/942872 [patent_app_country] => US [patent_app_date] => 2013-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 2957 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13942872 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/942872
Switch circuit Jul 15, 2013 Issued
Array ( [id] => 9558369 [patent_doc_number] => 20140176081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'BOOST CONTROL METHOD AND SYSTEM FOR BOOST CONVERTER' [patent_app_type] => utility [patent_app_number] => 13/942886 [patent_app_country] => US [patent_app_date] => 2013-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2787 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13942886 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/942886
BOOST CONTROL METHOD AND SYSTEM FOR BOOST CONVERTER Jul 15, 2013 Abandoned
Array ( [id] => 9118025 [patent_doc_number] => 20130284947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'METHOD AND SYSTEM FOR FORMING PATTERNS USING CHARGED PARTICLE BEAM LITHOGRAPHY WITH MULTIPLE EXPOSURE PASSES' [patent_app_type] => utility [patent_app_number] => 13/924019 [patent_app_country] => US [patent_app_date] => 2013-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11094 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13924019 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/924019
Method and system for forming patterns using charged particle beam lithography with multiple exposure passes Jun 20, 2013 Issued
Array ( [id] => 10085480 [patent_doc_number] => 09122828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-01 [patent_title] => 'Apparatus and method for designing an integrated circuit layout having a plurality of cell technologies' [patent_app_type] => utility [patent_app_number] => 13/896373 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3835 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13896373 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/896373
Apparatus and method for designing an integrated circuit layout having a plurality of cell technologies May 16, 2013 Issued
Array ( [id] => 9137380 [patent_doc_number] => 20130298095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'METHOD FOR CHECKING I/O CELL CONNECTIONS AND ASSOCIATED COMPUTER READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 13/875263 [patent_app_country] => US [patent_app_date] => 2013-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2657 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13875263 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/875263
METHOD FOR CHECKING I/O CELL CONNECTIONS AND ASSOCIATED COMPUTER READABLE MEDIUM Apr 30, 2013 Abandoned
Array ( [id] => 9137387 [patent_doc_number] => 20130298102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'Input Space Reduction for Verification Test Set Generation' [patent_app_type] => utility [patent_app_number] => 13/875143 [patent_app_country] => US [patent_app_date] => 2013-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7803 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13875143 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/875143
Input space reduction for verification test set generation Apr 30, 2013 Issued
Array ( [id] => 9947703 [patent_doc_number] => 08997032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-31 [patent_title] => 'Method for input/output design of chip' [patent_app_type] => utility [patent_app_number] => 13/863503 [patent_app_country] => US [patent_app_date] => 2013-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6129 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13863503 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/863503
Method for input/output design of chip Apr 15, 2013 Issued
Array ( [id] => 9118133 [patent_doc_number] => 20130285055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/857692 [patent_app_country] => US [patent_app_date] => 2013-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11420 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13857692 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/857692
Semiconductor device Apr 4, 2013 Issued
Array ( [id] => 11285737 [patent_doc_number] => 09501592 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-22 [patent_title] => 'Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language' [patent_app_type] => utility [patent_app_number] => 13/831943 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 15080 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13831943 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/831943
Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language Mar 14, 2013 Issued
Array ( [id] => 11179919 [patent_doc_number] => 09411912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-09 [patent_title] => 'Clock topology planning for reduced power consumption' [patent_app_type] => utility [patent_app_number] => 13/844683 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 68 [patent_no_of_words] => 31202 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13844683 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/844683
Clock topology planning for reduced power consumption Mar 14, 2013 Issued
Array ( [id] => 9746576 [patent_doc_number] => 20140282295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Method for Forming Photo-masks and OPC Method' [patent_app_type] => utility [patent_app_number] => 13/802833 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13802833 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/802833
Method for Forming Photo-masks and OPC Method Mar 13, 2013 Abandoned
Array ( [id] => 9746608 [patent_doc_number] => 20140282327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'CUTTER IN DIAGNOSIS (CID) A METHOD TO IMPROVE THE THROUGHPUT OF THE YIELD RAMP UP PROCESS' [patent_app_type] => utility [patent_app_number] => 13/830683 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7920 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13830683 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/830683
CUTTER IN DIAGNOSIS (CID) A METHOD TO IMPROVE THE THROUGHPUT OF THE YIELD RAMP UP PROCESS Mar 13, 2013 Abandoned
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