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Irina Kalish

Examiner (ID: 10416)

Most Active Art Unit
1714
Art Unit(s)
1714
Total Applications
6
Issued Applications
3
Pending Applications
0
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8604281 [patent_doc_number] => 20130009593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'CHARGER AND CHARGING APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/580845 [patent_app_country] => US [patent_app_date] => 2011-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7868 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13580845 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/580845
Charger and charging apparatus Jan 24, 2011 Issued
Array ( [id] => 6131623 [patent_doc_number] => 20110088006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'METHOD FOR LAYOUT VERIFICATION OF SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/970499 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 10584 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20110088006.pdf [firstpage_image] =>[orig_patent_app_number] => 12970499 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970499
METHOD FOR LAYOUT VERIFICATION OF SEMICONDUCTOR INTEGRATED CIRCUIT Dec 15, 2010 Abandoned
Array ( [id] => 10834854 [patent_doc_number] => 08863049 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-14 [patent_title] => 'Constraining traces in formal verification' [patent_app_type] => utility [patent_app_number] => 12/961389 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5528 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12961389 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/961389
Constraining traces in formal verification Dec 5, 2010 Issued
Array ( [id] => 9853152 [patent_doc_number] => 08954901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Parameter variation improvement' [patent_app_type] => utility [patent_app_number] => 12/958979 [patent_app_country] => US [patent_app_date] => 2010-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5365 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12958979 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/958979
Parameter variation improvement Dec 1, 2010 Issued
Array ( [id] => 8935829 [patent_doc_number] => 08495551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Shaping ports in integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/946179 [patent_app_country] => US [patent_app_date] => 2010-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 5825 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12946179 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/946179
Shaping ports in integrated circuit design Nov 14, 2010 Issued
Array ( [id] => 9392533 [patent_doc_number] => 08689158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'System and method for performing static timing analysis in the presence of correlations between asserted arrival times' [patent_app_type] => utility [patent_app_number] => 12/944059 [patent_app_country] => US [patent_app_date] => 2010-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5383 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12944059 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/944059
System and method for performing static timing analysis in the presence of correlations between asserted arrival times Nov 10, 2010 Issued
Array ( [id] => 10533973 [patent_doc_number] => 09259590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Tube-structured battery to be inserted into living body' [patent_app_type] => utility [patent_app_number] => 13/635244 [patent_app_country] => US [patent_app_date] => 2010-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 181 [patent_figures_cnt] => 181 [patent_no_of_words] => 61631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13635244 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/635244
Tube-structured battery to be inserted into living body Nov 4, 2010 Issued
Array ( [id] => 9940918 [patent_doc_number] => 08990751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Computer system and method of preparing a layout' [patent_app_type] => utility [patent_app_number] => 12/913949 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4587 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12913949 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/913949
Computer system and method of preparing a layout Oct 27, 2010 Issued
Array ( [id] => 8176969 [patent_doc_number] => 20120110531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'DEFECT AND YIELD PREDICTION FOR SEGMENTS OF AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/914849 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4554 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20120110531.pdf [firstpage_image] =>[orig_patent_app_number] => 12914849 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/914849
DEFECT AND YIELD PREDICTION FOR SEGMENTS OF AN INTEGRATED CIRCUIT Oct 27, 2010 Abandoned
Array ( [id] => 8849434 [patent_doc_number] => 08458634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Latch clustering with proximity to local clock buffers' [patent_app_type] => utility [patent_app_number] => 12/912919 [patent_app_country] => US [patent_app_date] => 2010-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6350 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12912919 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/912919
Latch clustering with proximity to local clock buffers Oct 26, 2010 Issued
Array ( [id] => 8414775 [patent_doc_number] => 20120242275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'LARGE-SCALE OCEAN MOBILE SOLAR POWER GENERATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/501272 [patent_app_country] => US [patent_app_date] => 2010-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9948 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13501272 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/501272
LARGE-SCALE OCEAN MOBILE SOLAR POWER GENERATION SYSTEM Oct 12, 2010 Abandoned
Array ( [id] => 7658578 [patent_doc_number] => 20110307847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'Hybrid system combining TLM simulators and HW accelerators' [patent_app_type] => utility [patent_app_number] => 12/802706 [patent_app_country] => US [patent_app_date] => 2010-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4616 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20110307847.pdf [firstpage_image] =>[orig_patent_app_number] => 12802706 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/802706
Hybrid system combining TLM simulators and HW accelerators Jun 9, 2010 Abandoned
Array ( [id] => 11252299 [patent_doc_number] => 09477802 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-25 [patent_title] => 'Isolating differences between revisions of a circuit design' [patent_app_type] => utility [patent_app_number] => 12/797476 [patent_app_country] => US [patent_app_date] => 2010-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 10029 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12797476 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/797476
Isolating differences between revisions of a circuit design Jun 8, 2010 Issued
Array ( [id] => 7653278 [patent_doc_number] => 20110302547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'METHOD AND APPARATUS FOR USING SCENARIO REDUCTION IN A CIRCUIT DESIGN FLOW' [patent_app_type] => utility [patent_app_number] => 12/795596 [patent_app_country] => US [patent_app_date] => 2010-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11696 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20110302547.pdf [firstpage_image] =>[orig_patent_app_number] => 12795596 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/795596
Performing scenario reduction in a circuit design flow Jun 6, 2010 Issued
Array ( [id] => 8878895 [patent_doc_number] => 08473880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-25 [patent_title] => 'Synchronization of parallel memory accesses in a dataflow circuit' [patent_app_type] => utility [patent_app_number] => 12/791256 [patent_app_country] => US [patent_app_date] => 2010-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5875 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12791256 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/791256
Synchronization of parallel memory accesses in a dataflow circuit May 31, 2010 Issued
Array ( [id] => 9458724 [patent_doc_number] => 08719751 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-06 [patent_title] => 'Simultaneous switching noise analysis' [patent_app_type] => utility [patent_app_number] => 12/789356 [patent_app_country] => US [patent_app_date] => 2010-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10765 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12789356 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/789356
Simultaneous switching noise analysis May 26, 2010 Issued
Array ( [id] => 6561134 [patent_doc_number] => 20100233877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'Method of disposing dummy pattern' [patent_app_type] => utility [patent_app_number] => 12/801114 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9493 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20100233877.pdf [firstpage_image] =>[orig_patent_app_number] => 12801114 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/801114
Method of disposing dummy pattern May 23, 2010 Abandoned
Array ( [id] => 7569409 [patent_doc_number] => 20110289472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'LAYOUT QUALITY EVALUATION' [patent_app_type] => utility [patent_app_number] => 12/782926 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5154 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20110289472.pdf [firstpage_image] =>[orig_patent_app_number] => 12782926 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782926
LAYOUT QUALITY EVALUATION May 18, 2010 Abandoned
Array ( [id] => 6652469 [patent_doc_number] => 20100229148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING' [patent_app_type] => utility [patent_app_number] => 12/781887 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7501 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20100229148.pdf [firstpage_image] =>[orig_patent_app_number] => 12781887 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/781887
METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING May 17, 2010 Abandoned
Array ( [id] => 10854373 [patent_doc_number] => 08881084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'FinFET boundary optimization' [patent_app_type] => utility [patent_app_number] => 12/780426 [patent_app_country] => US [patent_app_date] => 2010-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12780426 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/780426
FinFET boundary optimization May 13, 2010 Issued
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