Search

Irina Kalish

Examiner (ID: 10416)

Most Active Art Unit
1714
Art Unit(s)
1714
Total Applications
6
Issued Applications
3
Pending Applications
0
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7563099 [patent_doc_number] => 20110276933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'Method for Supporting Multiple Libraries Characterized at Different Process, Voltage, and Temperature Points' [patent_app_type] => utility [patent_app_number] => 12/774766 [patent_app_country] => US [patent_app_date] => 2010-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3953 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20110276933.pdf [firstpage_image] =>[orig_patent_app_number] => 12774766 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774766
Method for supporting multiple libraries characterized at different process, voltage and temperature points May 5, 2010 Issued
Array ( [id] => 6464939 [patent_doc_number] => 20100281448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'LOW-POWER FPGA CIRCUITS AND METHODS' [patent_app_type] => utility [patent_app_number] => 12/773686 [patent_app_country] => US [patent_app_date] => 2010-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 44474 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281448.pdf [firstpage_image] =>[orig_patent_app_number] => 12773686 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/773686
Low-power FPGA circuits and methods May 3, 2010 Issued
Array ( [id] => 6464991 [patent_doc_number] => 20100281452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'LAYOUT DESIGN METHOD, LAYOUT DESIGN PROGRAM, AND LAYOUT DESIGN APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/767186 [patent_app_country] => US [patent_app_date] => 2010-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6557 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281452.pdf [firstpage_image] =>[orig_patent_app_number] => 12767186 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/767186
LAYOUT DESIGN METHOD, LAYOUT DESIGN PROGRAM, AND LAYOUT DESIGN APPARATUS Apr 25, 2010 Abandoned
Array ( [id] => 6410591 [patent_doc_number] => 20100180253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'DEFECT PATTERN MATCHING AND VERIFICATION IN INTEGRATED CIRCUIT DESIGN AND MANUFACTURING' [patent_app_type] => utility [patent_app_number] => 12/748401 [patent_app_country] => US [patent_app_date] => 2010-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20100180253.pdf [firstpage_image] =>[orig_patent_app_number] => 12748401 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/748401
DEFECT PATTERN MATCHING AND VERIFICATION IN INTEGRATED CIRCUIT DESIGN AND MANUFACTURING Mar 26, 2010 Abandoned
Array ( [id] => 6410562 [patent_doc_number] => 20100180250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'METHOD AND APPARATUS FOR GENERATING LAYOUT REGIONS WITH LOCAL PREFERRED DIRECTIONS' [patent_app_type] => utility [patent_app_number] => 12/731078 [patent_app_country] => US [patent_app_date] => 2010-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10152 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20100180250.pdf [firstpage_image] =>[orig_patent_app_number] => 12731078 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/731078
Method and apparatus for generating layout regions with local preferred directions Mar 23, 2010 Issued
Array ( [id] => 6366658 [patent_doc_number] => 20100088257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'Systems and Methods for Generating Predicates and Assertions' [patent_app_type] => utility [patent_app_number] => 12/634586 [patent_app_country] => US [patent_app_date] => 2009-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5528 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20100088257.pdf [firstpage_image] =>[orig_patent_app_number] => 12634586 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/634586
Systems and Methods for Generating Predicates and Assertions Dec 8, 2009 Abandoned
Array ( [id] => 6554675 [patent_doc_number] => 20100125821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'Design support method' [patent_app_type] => utility [patent_app_number] => 12/588919 [patent_app_country] => US [patent_app_date] => 2009-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9061 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20100125821.pdf [firstpage_image] =>[orig_patent_app_number] => 12588919 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/588919
Design support method Nov 1, 2009 Abandoned
Array ( [id] => 6619516 [patent_doc_number] => 20100050142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'SPECIAL ENGINEERING CHANGE ORDER CELLS' [patent_app_type] => utility [patent_app_number] => 12/608469 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4652 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20100050142.pdf [firstpage_image] =>[orig_patent_app_number] => 12608469 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/608469
Special engineering change order cells Oct 28, 2009 Issued
Array ( [id] => 8472875 [patent_doc_number] => 08302067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Pin-out designation method for package-board codesign' [patent_app_type] => utility [patent_app_number] => 12/581259 [patent_app_country] => US [patent_app_date] => 2009-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 6463 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 434 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12581259 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/581259
Pin-out designation method for package-board codesign Oct 18, 2009 Issued
Array ( [id] => 9500247 [patent_doc_number] => 08739088 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-27 [patent_title] => 'Using constraints wtihin a high-level modeling system for circuit design' [patent_app_type] => utility [patent_app_number] => 12/581104 [patent_app_country] => US [patent_app_date] => 2009-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 8580 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12581104 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/581104
Using constraints wtihin a high-level modeling system for circuit design Oct 15, 2009 Issued
Array ( [id] => 6466018 [patent_doc_number] => 20100146470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'METHOD AND SYSTEM FOR VOLTAGE FLUCTUATION AMOUNT CALCULATION' [patent_app_type] => utility [patent_app_number] => 12/580829 [patent_app_country] => US [patent_app_date] => 2009-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5655 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20100146470.pdf [firstpage_image] =>[orig_patent_app_number] => 12580829 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/580829
Method and system for voltage fluctuation amount calculation Oct 15, 2009 Issued
Array ( [id] => 6131629 [patent_doc_number] => 20110088008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'METHOD FOR CONVERSION OF COMMERCIAL MICROPROCESSOR TO RADIATION-HARDENED PROCESSOR AND RESULTING PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/579159 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7917 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20110088008.pdf [firstpage_image] =>[orig_patent_app_number] => 12579159 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/579159
METHOD FOR CONVERSION OF COMMERCIAL MICROPROCESSOR TO RADIATION-HARDENED PROCESSOR AND RESULTING PROCESSOR Oct 13, 2009 Abandoned
Array ( [id] => 6154301 [patent_doc_number] => 20110023001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'DYNAMIC RULE CHECKING IN ELECTRONIC DESIGN AUTOMATION' [patent_app_type] => utility [patent_app_number] => 12/579309 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4449 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20110023001.pdf [firstpage_image] =>[orig_patent_app_number] => 12579309 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/579309
Dynamic rule checking in electronic design automation Oct 13, 2009 Issued
Array ( [id] => 9326341 [patent_doc_number] => 08661378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Asychronous system analysis' [patent_app_type] => utility [patent_app_number] => 12/570629 [patent_app_country] => US [patent_app_date] => 2009-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4957 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12570629 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/570629
Asychronous system analysis Sep 29, 2009 Issued
Array ( [id] => 6389558 [patent_doc_number] => 20100083206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'Clock signal providing circuit designing method, information processing apparatus and computer-readable information recording medium' [patent_app_type] => utility [patent_app_number] => 12/585959 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 13992 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20100083206.pdf [firstpage_image] =>[orig_patent_app_number] => 12585959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585959
Clock signal providing circuit designing method, information processing apparatus and computer-readable information recording medium Sep 28, 2009 Abandoned
Array ( [id] => 6527380 [patent_doc_number] => 20100262409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'BLENDED MODEL INTERPOLATION' [patent_app_type] => utility [patent_app_number] => 12/420879 [patent_app_country] => US [patent_app_date] => 2009-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5305 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20100262409.pdf [firstpage_image] =>[orig_patent_app_number] => 12420879 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/420879
Blended model interpolation Apr 8, 2009 Issued
Array ( [id] => 8899599 [patent_doc_number] => 08479133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Method of and circuit for implementing a filter in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/418979 [patent_app_country] => US [patent_app_date] => 2009-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 11011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12418979 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/418979
Method of and circuit for implementing a filter in an integrated circuit Apr 5, 2009 Issued
Array ( [id] => 8285831 [patent_doc_number] => 08219950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Propagation delay time balancing in chained inverting devices' [patent_app_type] => utility [patent_app_number] => 12/382689 [patent_app_country] => US [patent_app_date] => 2009-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5045 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12382689 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/382689
Propagation delay time balancing in chained inverting devices Mar 19, 2009 Issued
Array ( [id] => 5476106 [patent_doc_number] => 20090249272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'STATISTICAL TIMING ANALYZER AND STATISTICAL TIMING ANALYSIS METHOD' [patent_app_type] => utility [patent_app_number] => 12/400819 [patent_app_country] => US [patent_app_date] => 2009-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20090249272.pdf [firstpage_image] =>[orig_patent_app_number] => 12400819 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/400819
STATISTICAL TIMING ANALYZER AND STATISTICAL TIMING ANALYSIS METHOD Mar 9, 2009 Abandoned
Array ( [id] => 6652452 [patent_doc_number] => 20100229143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'DETECTION AND REMOVAL OF HAZARDS DURING OPTIMIZATION OF LOGIC CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/399119 [patent_app_country] => US [patent_app_date] => 2009-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8978 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20100229143.pdf [firstpage_image] =>[orig_patent_app_number] => 12399119 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/399119
Detection and removal of hazards during optimization of logic circuits Mar 5, 2009 Issued
Menu