Search

Ishrat I. Sherali

Examiner (ID: 11892)

Most Active Art Unit
2667
Art Unit(s)
2667, 2624, 2621, 2721
Total Applications
1820
Issued Applications
1614
Pending Applications
130
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18081183 [patent_doc_number] => 20220406795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE WITH DIVIDED DRAIN SELECT GATE LINES AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/483049 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483049 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483049
THREE-DIMENSIONAL MEMORY DEVICE WITH DIVIDED DRAIN SELECT GATE LINES AND METHOD FOR FORMING THE SAME Sep 22, 2021 Pending
Array ( [id] => 17566750 [patent_doc_number] => 20220130899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => INTEGRATED MEMS-CMOS ULTRASONIC SENSOR [patent_app_type] => utility [patent_app_number] => 17/477498 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477498 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477498
INTEGRATED MEMS-CMOS ULTRASONIC SENSOR Sep 15, 2021 Abandoned
Array ( [id] => 17562172 [patent_doc_number] => 20220126321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => ULTRASONIC SENSOR WITH INTEGRATED THERMAL STABILIZATION [patent_app_type] => utility [patent_app_number] => 17/477509 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477509
ULTRASONIC SENSOR WITH INTEGRATED THERMAL STABILIZATION Sep 15, 2021 Abandoned
Array ( [id] => 19966683 [patent_doc_number] => 12336221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/475562 [patent_app_country] => US [patent_app_date] => 2021-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 1074 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 469 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17475562 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/475562
Semiconductor device Sep 14, 2021 Issued
Array ( [id] => 17963752 [patent_doc_number] => 20220344333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => FIELD EFFECT TRANSISTOR AND METHOD [patent_app_type] => utility [patent_app_number] => 17/476418 [patent_app_country] => US [patent_app_date] => 2021-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10929 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476418 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/476418
FIELD EFFECT TRANSISTOR AND METHOD Sep 14, 2021 Pending
Array ( [id] => 20205614 [patent_doc_number] => 12408410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Silicon carbide device with stripe-shaped gate electrode and source metallization [patent_app_type] => utility [patent_app_number] => 17/473917 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 31 [patent_no_of_words] => 2320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/473917
Silicon carbide device with stripe-shaped gate electrode and source metallization Sep 12, 2021 Issued
Array ( [id] => 17477656 [patent_doc_number] => 20220085160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/470561 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6128 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470561 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470561
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Sep 8, 2021 Pending
Array ( [id] => 17477704 [patent_doc_number] => 20220085208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/470592 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470592 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470592
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE Sep 8, 2021 Abandoned
Array ( [id] => 17303264 [patent_doc_number] => 20210399103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => CONTROL GATE STRAP LAYOUT TO IMPROVE A WORD LINE ETCH PROCESS WINDOW [patent_app_type] => utility [patent_app_number] => 17/462444 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462444 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462444
Control gate strap layout to improve a word line etch process window Aug 30, 2021 Issued
Array ( [id] => 18211906 [patent_doc_number] => 20230058170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => MEMORY DEVICE STRUCTURE AND FORMING METHOD INCLUDING RETICLE ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 17/404649 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17404649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/404649
MEMORY DEVICE STRUCTURE AND FORMING METHOD INCLUDING RETICLE ADJUSTMENT Aug 16, 2021 Pending
Array ( [id] => 17723557 [patent_doc_number] => 20220216279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/402428 [patent_app_country] => US [patent_app_date] => 2021-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/402428
DISPLAY DEVICE Aug 12, 2021 Pending
Array ( [id] => 17645502 [patent_doc_number] => 20220173241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/400345 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/400345
Semiconductor device and method of manufacturing the same Aug 11, 2021 Issued
Array ( [id] => 17347302 [patent_doc_number] => 20220013633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => SEMICONDUCTOR DEVICE AND CHIP SINGULATION METHOD [patent_app_type] => utility [patent_app_number] => 17/399869 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399869 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399869
Semiconductor device and chip singulation method Aug 10, 2021 Issued
Array ( [id] => 19277485 [patent_doc_number] => 12027618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/395910 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5844 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 498 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395910 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395910
Semiconductor device Aug 5, 2021 Issued
Array ( [id] => 17217942 [patent_doc_number] => 20210351280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/385011 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17385011 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/385011
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME Jul 25, 2021 Abandoned
Array ( [id] => 17203838 [patent_doc_number] => 20210343933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => MAGNETIC TUNNEL JUNCTION STRUCTURES AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/374799 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17374799 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/374799
Magnetic tunnel junction structures and related methods Jul 12, 2021 Issued
Array ( [id] => 17204208 [patent_doc_number] => 20210344303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => HIGH-IMPLANT CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/373629 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17373629 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/373629
High-implant channel semiconductor device and method for manufacturing the same Jul 11, 2021 Issued
Array ( [id] => 17389670 [patent_doc_number] => 20220037522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => TRENCH MOSFET AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/370124 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370124 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370124
TRENCH MOSFET AND METHOD FOR MANUFACTURING THE SAME Jul 7, 2021 Abandoned
Array ( [id] => 17188790 [patent_doc_number] => 20210335675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => SEMICONDUCTOR STRUCTURE WITH BURIED POWER RAIL, INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/369633 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369633 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369633
Semiconductor structure with buried power rail, integrated circuit and method for manufacturing the semiconductor structure Jul 6, 2021 Issued
Array ( [id] => 18124716 [patent_doc_number] => 20230010328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => SHIELDED GATE TRENCH MOSFET WITH MULTIPLE STEPPED EPITAXIAL STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/367662 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17367662 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/367662
SHIELDED GATE TRENCH MOSFET WITH MULTIPLE STEPPED EPITAXIAL STRUCTURES Jul 5, 2021 Abandoned
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