
Ishwarbhai B. Patel
Examiner (ID: 1775, Phone: (571)272-1933 , Office: P/2847 )
| Most Active Art Unit | 2847 |
| Art Unit(s) | 2827, 2847, 2835, 2841 |
| Total Applications | 1757 |
| Issued Applications | 1164 |
| Pending Applications | 46 |
| Abandoned Applications | 568 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8538623
[patent_doc_number] => 08314344
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-11-20
[patent_title] => 'Wiring board and manufacturing method of the same'
[patent_app_type] => utility
[patent_app_number] => 12/573256
[patent_app_country] => US
[patent_app_date] => 2009-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 15520
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 255
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12573256
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/573256 | Wiring board and manufacturing method of the same | Oct 4, 2009 | Issued |
Array
(
[id] => 8543822
[patent_doc_number] => 08319115
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-11-27
[patent_title] => 'Wiring board and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/562956
[patent_app_country] => US
[patent_app_date] => 2009-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12562956
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/562956 | Wiring board and manufacturing method thereof | Sep 17, 2009 | Issued |
Array
(
[id] => 5460921
[patent_doc_number] => 20090321121
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-31
[patent_title] => 'CERAMIC MULTILAYER SUBSTRATE AND ITS MANUFACTURING METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/552389
[patent_app_country] => US
[patent_app_date] => 2009-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => publications/A1/0321/20090321121.pdf
[firstpage_image] =>[orig_patent_app_number] => 12552389
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/552389 | CERAMIC MULTILAYER SUBSTRATE AND ITS MANUFACTURING METHOD | Sep 1, 2009 | Abandoned |
Array
(
[id] => 6495442
[patent_doc_number] => 20100012357
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-21
[patent_title] => 'Printed Circuit Board With Improved Via Design'
[patent_app_type] => utility
[patent_app_number] => 12/548933
[patent_app_country] => US
[patent_app_date] => 2009-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] => publications/A1/0012/20100012357.pdf
[firstpage_image] =>[orig_patent_app_number] => 12548933
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/548933 | Printed circuit board with improved via design | Aug 26, 2009 | Issued |
Array
(
[id] => 6214741
[patent_doc_number] => 20100051341
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-04
[patent_title] => 'Circuit substrate having power/ground plane with grid holes'
[patent_app_type] => utility
[patent_app_number] => 12/583804
[patent_app_country] => US
[patent_app_date] => 2009-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0051/20100051341.pdf
[firstpage_image] =>[orig_patent_app_number] => 12583804
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/583804 | Circuit substrate having power/ground plane with grid holes | Aug 25, 2009 | Issued |
Array
(
[id] => 6129115
[patent_doc_number] => 20110005824
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-01-13
[patent_title] => 'PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/544100
[patent_app_country] => US
[patent_app_date] => 2009-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0005/20110005824.pdf
[firstpage_image] =>[orig_patent_app_number] => 12544100
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/544100 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME | Aug 18, 2009 | Abandoned |
Array
(
[id] => 9009743
[patent_doc_number] => 08525041
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-03
[patent_title] => 'Multilayer wiring board and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/543644
[patent_app_country] => US
[patent_app_date] => 2009-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12543644
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Array
(
[id] => 5364216
[patent_doc_number] => 20090301775
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-10
[patent_title] => 'Wired circuit board and electronic device'
[patent_app_type] => utility
[patent_app_number] => 12/461576
[patent_app_country] => US
[patent_app_date] => 2009-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 12973
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[pdf_file] => publications/A1/0301/20090301775.pdf
[firstpage_image] =>[orig_patent_app_number] => 12461576
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/461576 | Wired circuit board and electronic device | Aug 16, 2009 | Abandoned |
Array
(
[id] => 8876188
[patent_doc_number] => 08471154
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-06-25
[patent_title] => 'Stackable variable height via package and method'
[patent_app_type] => utility
[patent_app_number] => 12/537048
[patent_app_country] => US
[patent_app_date] => 2009-08-06
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12537048
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/537048 | Stackable variable height via package and method | Aug 5, 2009 | Issued |
Array
(
[id] => 6627952
[patent_doc_number] => 20100035021
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-11
[patent_title] => 'Method of manufacturing a substrate, substrate, device provided with a substrate, and determining method'
[patent_app_type] => utility
[patent_app_number] => 12/461268
[patent_app_country] => US
[patent_app_date] => 2009-08-05
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[patent_drawing_sheets_cnt] => 4
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[pdf_file] => publications/A1/0035/20100035021.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/461268 | Method of manufacturing a substrate, substrate, device provided with a substrate, and determining method | Aug 4, 2009 | Issued |
Array
(
[id] => 4600400
[patent_doc_number] => 07977578
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-12
[patent_title] => 'Tab tape for tape carrier package'
[patent_app_type] => utility
[patent_app_number] => 12/458936
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[pdf_file] => patents/07/977/07977578.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/458936 | Tab tape for tape carrier package | Jul 27, 2009 | Issued |
Array
(
[id] => 6147617
[patent_doc_number] => 20110019375
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[patent_kind] => A1
[patent_issue_date] => 2011-01-27
[patent_title] => 'Z-DIRECTED PASS-THROUGH COMPONENTS FOR PRINTED CIRCUIT BOARDS'
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[patent_app_number] => 12/508145
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[firstpage_image] =>[orig_patent_app_number] => 12508145
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/508145 | Z-directed pass-through components for printed circuit boards | Jul 22, 2009 | Issued |
Array
(
[id] => 8858925
[patent_doc_number] => 08461460
[patent_country] => US
[patent_kind] => B2
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[patent_title] => 'Microelectronic interconnect element with decreased conductor spacing'
[patent_app_type] => utility
[patent_app_number] => 12/459864
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Array
(
[id] => 8115341
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Array
(
[id] => 4610102
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Array
(
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Array
(
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Array
(
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Array
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Array
(
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[firstpage_image] =>[orig_patent_app_number] => 12475728
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/475728 | Heat sink arrangement for electrical apparatus | May 31, 2009 | Issued |