Search

Ishwarbhai B. Patel

Examiner (ID: 13112, Phone: (571)272-1933 , Office: P/2847 )

Most Active Art Unit
2847
Art Unit(s)
2841, 2827, 2835, 2847
Total Applications
1782
Issued Applications
1162
Pending Applications
78
Abandoned Applications
569

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4775284 [patent_doc_number] => 20080283282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'MULTI-LAYER PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING MULTI-LAYER PRINTED CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 12/179201 [patent_app_country] => US [patent_app_date] => 2008-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 17018 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20080283282.pdf [firstpage_image] =>[orig_patent_app_number] => 12179201 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/179201
Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board Jul 23, 2008 Issued
Array ( [id] => 11413442 [patent_doc_number] => 09560772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Electric circuit configuration having an MID circuit carrier and a connecting interface connected to it' [patent_app_type] => utility [patent_app_number] => 12/674129 [patent_app_country] => US [patent_app_date] => 2008-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 4635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12674129 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/674129
Electric circuit configuration having an MID circuit carrier and a connecting interface connected to it Jul 17, 2008 Issued
Array ( [id] => 8446611 [patent_doc_number] => 08288664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Multi-layer printed circuit board and method of manufacturing multilayer printed circuit board' [patent_app_type] => utility [patent_app_number] => 12/171794 [patent_app_country] => US [patent_app_date] => 2008-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 70 [patent_no_of_words] => 31150 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12171794 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/171794
Multi-layer printed circuit board and method of manufacturing multilayer printed circuit board Jul 10, 2008 Issued
Array ( [id] => 9074726 [patent_doc_number] => 08552306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Assembly and production of an assembly' [patent_app_type] => utility [patent_app_number] => 12/671153 [patent_app_country] => US [patent_app_date] => 2008-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2087 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12671153 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/671153
Assembly and production of an assembly Jul 3, 2008 Issued
Array ( [id] => 6119859 [patent_doc_number] => 20110083889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'FPC-Based Relay Connector' [patent_app_type] => utility [patent_app_number] => 12/666065 [patent_app_country] => US [patent_app_date] => 2008-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20110083889.pdf [firstpage_image] =>[orig_patent_app_number] => 12666065 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/666065
FPC-Based Relay Connector Jun 24, 2008 Abandoned
Array ( [id] => 4680919 [patent_doc_number] => 20080247145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'INTEGRATED CIRCUIT CARRIER ARRANGEMENT WITH ELECTRICAL CONNECTION ISLANDS' [patent_app_type] => utility [patent_app_number] => 12/141037 [patent_app_country] => US [patent_app_date] => 2008-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3289 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20080247145.pdf [firstpage_image] =>[orig_patent_app_number] => 12141037 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/141037
Integrated circuit carrier arrangement with electrical connection islands Jun 16, 2008 Issued
Array ( [id] => 8146989 [patent_doc_number] => 08164000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Flexible printed circuit boards including carbon nanotube bundles' [patent_app_type] => utility [patent_app_number] => 12/135849 [patent_app_country] => US [patent_app_date] => 2008-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 2437 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/164/08164000.pdf [firstpage_image] =>[orig_patent_app_number] => 12135849 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/135849
Flexible printed circuit boards including carbon nanotube bundles Jun 8, 2008 Issued
Array ( [id] => 4707525 [patent_doc_number] => 20080296051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'PRINTED CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 12/127364 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4919 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20080296051.pdf [firstpage_image] =>[orig_patent_app_number] => 12127364 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127364
PRINTED CIRCUIT BOARD May 26, 2008 Abandoned
Array ( [id] => 9026882 [patent_doc_number] => 08536464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Multilayer substrate' [patent_app_type] => utility [patent_app_number] => 12/994774 [patent_app_country] => US [patent_app_date] => 2008-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 2879 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12994774 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/994774
Multilayer substrate May 25, 2008 Issued
Array ( [id] => 4634803 [patent_doc_number] => 08013255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Printed circuit board with high density differential pairs' [patent_app_type] => utility [patent_app_number] => 12/126748 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1105 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/013/08013255.pdf [firstpage_image] =>[orig_patent_app_number] => 12126748 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/126748
Printed circuit board with high density differential pairs May 22, 2008 Issued
Array ( [id] => 4707526 [patent_doc_number] => 20080296052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'MULTILAYER PRINTED WIRING BOARD' [patent_app_type] => utility [patent_app_number] => 12/124635 [patent_app_country] => US [patent_app_date] => 2008-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 18955 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20080296052.pdf [firstpage_image] =>[orig_patent_app_number] => 12124635 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/124635
MULTILAYER PRINTED WIRING BOARD May 20, 2008 Abandoned
Array ( [id] => 4816351 [patent_doc_number] => 20080223610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'BGA PACKAGE SUBSTRATE AND METHOD OF FABRICATING SAME' [patent_app_type] => utility [patent_app_number] => 12/116679 [patent_app_country] => US [patent_app_date] => 2008-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6069 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20080223610.pdf [firstpage_image] =>[orig_patent_app_number] => 12116679 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/116679
BGA PACKAGE SUBSTRATE AND METHOD OF FABRICATING SAME May 6, 2008 Abandoned
Array ( [id] => 4885249 [patent_doc_number] => 20080259581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Circuitized substrates utilizing smooth-sided conductive layers as part thereof' [patent_app_type] => utility [patent_app_number] => 12/148271 [patent_app_country] => US [patent_app_date] => 2008-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7798 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20080259581.pdf [firstpage_image] =>[orig_patent_app_number] => 12148271 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/148271
Circuitized substrates utilizing smooth-sided conductive layers as part thereof Apr 16, 2008 Issued
Array ( [id] => 4811822 [patent_doc_number] => 20080192453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'MULTILAYER INTERCONNECTION SUBSTRATE AND MANUFACTURING METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 12/099450 [patent_app_country] => US [patent_app_date] => 2008-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3585 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20080192453.pdf [firstpage_image] =>[orig_patent_app_number] => 12099450 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/099450
Multilayer interconnection substrate and manufacturing method therefor Apr 7, 2008 Issued
Array ( [id] => 4707530 [patent_doc_number] => 20080296056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'Printed circuit board, production method therefor, electronic-component carrier board using printed circuit board, and production method therefor' [patent_app_type] => utility [patent_app_number] => 12/079055 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4768 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20080296056.pdf [firstpage_image] =>[orig_patent_app_number] => 12079055 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/079055
Printed circuit board, production method therefor, electronic-component carrier board using printed circuit board, and production method therefor Mar 23, 2008 Abandoned
Array ( [id] => 6601639 [patent_doc_number] => 20100309641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'INTERPOSER SUBSTRATE, LSI CHIP AND INFORMATION TERMINAL DEVICE USING THE INTERPOSER SUBSTRATE, MANUFACTURING METHOD OF INTERPOSER SUBSTRATE, AND MANUFACTURING METHOD OF LSI CHIP' [patent_app_type] => utility [patent_app_number] => 12/521602 [patent_app_country] => US [patent_app_date] => 2008-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5623 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0309/20100309641.pdf [firstpage_image] =>[orig_patent_app_number] => 12521602 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/521602
INTERPOSER SUBSTRATE, LSI CHIP AND INFORMATION TERMINAL DEVICE USING THE INTERPOSER SUBSTRATE, MANUFACTURING METHOD OF INTERPOSER SUBSTRATE, AND MANUFACTURING METHOD OF LSI CHIP Mar 20, 2008 Abandoned
Array ( [id] => 8713638 [patent_doc_number] => 08399778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Circuit board structure and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 12/047868 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3130 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12047868 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/047868
Circuit board structure and fabrication method thereof Mar 12, 2008 Issued
Array ( [id] => 4736612 [patent_doc_number] => 20080230264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'INTERCONNECTION STRUCTURE AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/045362 [patent_app_country] => US [patent_app_date] => 2008-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3008 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20080230264.pdf [firstpage_image] =>[orig_patent_app_number] => 12045362 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/045362
INTERCONNECTION STRUCTURE AND METHOD THEREOF Mar 9, 2008 Abandoned
Array ( [id] => 10127070 [patent_doc_number] => 09161447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Embedded capacitive stack' [patent_app_type] => utility [patent_app_number] => 12/045660 [patent_app_country] => US [patent_app_date] => 2008-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 13818 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12045660 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/045660
Embedded capacitive stack Mar 9, 2008 Issued
Array ( [id] => 4952153 [patent_doc_number] => 20080185177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'CIRCUIT BOARD STRUCTURE FOR ELECTRICAL TESTING AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/045140 [patent_app_country] => US [patent_app_date] => 2008-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2860 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20080185177.pdf [firstpage_image] =>[orig_patent_app_number] => 12045140 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/045140
Circuit board structure for electrical testing and fabrication method thereof Mar 9, 2008 Issued
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