| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 1515871
[patent_doc_number] => 06420658
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-16
[patent_title] => 'Module circuit board for semiconductor device having barriers to isolate I/O terminals from solder'
[patent_app_type] => B1
[patent_app_number] => 09/450504
[patent_app_country] => US
[patent_app_date] => 1999-11-30
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[pdf_file] => patents/06/420/06420658.pdf
[firstpage_image] =>[orig_patent_app_number] => 09450504
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/450504 | Module circuit board for semiconductor device having barriers to isolate I/O terminals from solder | Nov 29, 1999 | Issued |
Array
(
[id] => 7639924
[patent_doc_number] => 06395992
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-28
[patent_title] => 'Three-dimensional wiring board and electric insulating member for wiring board'
[patent_app_type] => B1
[patent_app_number] => 09/449654
[patent_app_country] => US
[patent_app_date] => 1999-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/395/06395992.pdf
[firstpage_image] =>[orig_patent_app_number] => 09449654
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/449654 | Three-dimensional wiring board and electric insulating member for wiring board | Nov 29, 1999 | Issued |
| 09/424567 | PROCESS FOR CONNECTING AN INTEGRATED CIRCUIT TO A CSP AND RESULTANT CHIP PACKAGE ASSEMBLY | Nov 23, 1999 | Abandoned |
Array
(
[id] => 1508965
[patent_doc_number] => 06441313
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-27
[patent_title] => 'Printed circuit board employing lossy power distribution network to reduce power plane resonances'
[patent_app_type] => B1
[patent_app_number] => 09/447513
[patent_app_country] => US
[patent_app_date] => 1999-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[pdf_file] => patents/06/441/06441313.pdf
[firstpage_image] =>[orig_patent_app_number] => 09447513
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/447513 | Printed circuit board employing lossy power distribution network to reduce power plane resonances | Nov 22, 1999 | Issued |
Array
(
[id] => 4316704
[patent_doc_number] => 06316731
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-13
[patent_title] => 'Method of forming a printed wiring board with compensation scales'
[patent_app_type] => 1
[patent_app_number] => 9/442382
[patent_app_country] => US
[patent_app_date] => 1999-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_claims] => 22
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[pdf_file] => patents/06/316/06316731.pdf
[firstpage_image] =>[orig_patent_app_number] => 442382
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/442382 | Method of forming a printed wiring board with compensation scales | Nov 16, 1999 | Issued |
Array
(
[id] => 4340085
[patent_doc_number] => 06333471
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-25
[patent_title] => 'Sheet metal component for double pattern conduction and printed circuit board'
[patent_app_type] => 1
[patent_app_number] => 9/441203
[patent_app_country] => US
[patent_app_date] => 1999-11-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/333/06333471.pdf
[firstpage_image] =>[orig_patent_app_number] => 441203
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/441203 | Sheet metal component for double pattern conduction and printed circuit board | Nov 15, 1999 | Issued |
| 09/437882 | CURRENT CARRYING STRUCTURE USING VOLTAGE SWITCHABLE DIELECTRIC MATERIAL | Nov 9, 1999 | Abandoned |
Array
(
[id] => 4325371
[patent_doc_number] => 06331678
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[patent_kind] => NA
[patent_issue_date] => 2001-12-18
[patent_title] => 'Reduction of blistering and delamination of high-temperature devices with metal film'
[patent_app_type] => 1
[patent_app_number] => 9/429051
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[firstpage_image] =>[orig_patent_app_number] => 429051
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/429051 | Reduction of blistering and delamination of high-temperature devices with metal film | Oct 28, 1999 | Issued |
Array
(
[id] => 1587467
[patent_doc_number] => 06359233
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-19
[patent_title] => 'Printed circuit board multipack structure having internal gold fingers and multipack and printed circuit board formed therefrom, and methods of manufacture thereof'
[patent_app_type] => B1
[patent_app_number] => 09/426758
[patent_app_country] => US
[patent_app_date] => 1999-10-26
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/359/06359233.pdf
[firstpage_image] =>[orig_patent_app_number] => 09426758
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/426758 | Printed circuit board multipack structure having internal gold fingers and multipack and printed circuit board formed therefrom, and methods of manufacture thereof | Oct 25, 1999 | Issued |
Array
(
[id] => 1524702
[patent_doc_number] => 06353189
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-05
[patent_title] => 'Wiring board, wiring board fabrication method, and semiconductor package'
[patent_app_type] => B1
[patent_app_number] => 09/403223
[patent_app_country] => US
[patent_app_date] => 1999-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
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[patent_no_of_words] => 18011
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[pdf_file] => patents/06/353/06353189.pdf
[firstpage_image] =>[orig_patent_app_number] => 09403223
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/403223 | Wiring board, wiring board fabrication method, and semiconductor package | Oct 14, 1999 | Issued |
Array
(
[id] => 4375165
[patent_doc_number] => 06288343
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-11
[patent_title] => 'Printed circuit board'
[patent_app_type] => 1
[patent_app_number] => 9/414818
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[patent_app_date] => 1999-10-08
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[firstpage_image] =>[orig_patent_app_number] => 414818
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/414818 | Printed circuit board | Oct 7, 1999 | Issued |
Array
(
[id] => 4386212
[patent_doc_number] => 06294743
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'Multilayer print circuit board and the production method of the multilayer print circuit board'
[patent_app_type] => 1
[patent_app_number] => 9/413147
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[firstpage_image] =>[orig_patent_app_number] => 413147
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/413147 | Multilayer print circuit board and the production method of the multilayer print circuit board | Oct 5, 1999 | Issued |
Array
(
[id] => 4386245
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Array
(
[id] => 4413239
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Array
(
[id] => 4409997
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[patent_issue_date] => 2001-05-15
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[patent_app_number] => 9/406717
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[firstpage_image] =>[orig_patent_app_number] => 406717
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/406717 | Hybrid integrated circuit device | Sep 27, 1999 | Issued |
| 09/399039 | SURFACE MOUNT PACKAGE FOR LONG LEAD DEVICES | Sep 20, 1999 | Abandoned |
Array
(
[id] => 4371874
[patent_doc_number] => 06274821
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-14
[patent_title] => 'Shock-resistive printed circuit board and electronic device including the same'
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[firstpage_image] =>[orig_patent_app_number] => 396426
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/396426 | Shock-resistive printed circuit board and electronic device including the same | Sep 14, 1999 | Issued |
Array
(
[id] => 1552360
[patent_doc_number] => 06399889
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'Head interconnect circuit with alignment finger'
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[firstpage_image] =>[orig_patent_app_number] => 09394153
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/394153 | Head interconnect circuit with alignment finger | Sep 12, 1999 | Issued |
Array
(
[id] => 4316792
[patent_doc_number] => 06316737
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-13
[patent_title] => 'Making a connection between a component and a circuit board'
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[firstpage_image] =>[orig_patent_app_number] => 393952
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/393952 | Making a connection between a component and a circuit board | Sep 8, 1999 | Issued |
Array
(
[id] => 4371840
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[patent_kind] => NA
[patent_issue_date] => 2001-08-14
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[firstpage_image] =>[orig_patent_app_number] => 387808
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/387808 | Method and article for the connection and repair of flex and other circuits | Aug 31, 1999 | Issued |