Ismael Izaguirre
Examiner (ID: 255, Phone: (571)272-4987 , Office: P/3765 )
Most Active Art Unit | 3765 |
Art Unit(s) | 2899, 3741, 3732, 2407, 3765, 3742, 3408 |
Total Applications | 3433 |
Issued Applications | 2991 |
Pending Applications | 109 |
Abandoned Applications | 333 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4357817
[patent_doc_number] => 06255141
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-03
[patent_title] => 'Method of packaging fuses'
[patent_app_type] => 1
[patent_app_number] => 9/391137
[patent_app_country] => US
[patent_app_date] => 1999-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 2163
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/255/06255141.pdf
[firstpage_image] =>[orig_patent_app_number] => 391137
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/391137 | Method of packaging fuses | Sep 6, 1999 | Issued |
Array
(
[id] => 1462412
[patent_doc_number] => 06350629
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Optical semiconductor device having active layer and carrier recombination layer different from each other'
[patent_app_type] => B1
[patent_app_number] => 09/386873
[patent_app_country] => US
[patent_app_date] => 1999-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 50
[patent_no_of_words] => 5080
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 249
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/350/06350629.pdf
[firstpage_image] =>[orig_patent_app_number] => 09386873
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/386873 | Optical semiconductor device having active layer and carrier recombination layer different from each other | Aug 30, 1999 | Issued |
Array
(
[id] => 5885882
[patent_doc_number] => 20020011666
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-31
[patent_title] => 'SELECTIVELY COATING BOND PADS'
[patent_app_type] => new
[patent_app_number] => 09/382930
[patent_app_country] => US
[patent_app_date] => 1999-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1645
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0011/20020011666.pdf
[firstpage_image] =>[orig_patent_app_number] => 09382930
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/382930 | Selectively coating bond pads | Aug 24, 1999 | Issued |
Array
(
[id] => 4336311
[patent_doc_number] => 06333227
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-25
[patent_title] => 'Methods of forming hemispherical grain silicon electrodes by crystallizing the necks thereof'
[patent_app_type] => 1
[patent_app_number] => 9/378682
[patent_app_country] => US
[patent_app_date] => 1999-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 4850
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/333/06333227.pdf
[firstpage_image] =>[orig_patent_app_number] => 378682
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/378682 | Methods of forming hemispherical grain silicon electrodes by crystallizing the necks thereof | Aug 19, 1999 | Issued |
Array
(
[id] => 4382088
[patent_doc_number] => 06277765
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-21
[patent_title] => 'Low-K Dielectric layer and method of making same'
[patent_app_type] => 1
[patent_app_number] => 9/376510
[patent_app_country] => US
[patent_app_date] => 1999-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3138
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/277/06277765.pdf
[firstpage_image] =>[orig_patent_app_number] => 376510
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/376510 | Low-K Dielectric layer and method of making same | Aug 16, 1999 | Issued |
09/359961 | SEMICONDUCTOR PACKAGE INCLUDING A NON-CONDUCTIVE ADHESIVE TAPE, AND METHOD AND APPARATUS FOR DIE BONDING | Jul 21, 1999 | Abandoned |
Array
(
[id] => 1108876
[patent_doc_number] => 06809350
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-10-26
[patent_title] => 'Quantum well detector with layer for the storage of photo-excited electrons'
[patent_app_type] => B1
[patent_app_number] => 09/328391
[patent_app_country] => US
[patent_app_date] => 1999-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 3884
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/809/06809350.pdf
[firstpage_image] =>[orig_patent_app_number] => 09328391
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/328391 | Quantum well detector with layer for the storage of photo-excited electrons | Jun 8, 1999 | Issued |
Array
(
[id] => 1441105
[patent_doc_number] => 06335292
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-01
[patent_title] => 'Method of controlling striations and CD loss in contact oxide etch'
[patent_app_type] => B1
[patent_app_number] => 09/292393
[patent_app_country] => US
[patent_app_date] => 1999-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 3575
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/335/06335292.pdf
[firstpage_image] =>[orig_patent_app_number] => 09292393
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/292393 | Method of controlling striations and CD loss in contact oxide etch | Apr 14, 1999 | Issued |
Array
(
[id] => 6000002
[patent_doc_number] => 20020028545
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-07
[patent_title] => 'HIGHLY RESISTIVE STATIC RANDOM ACCESS MEMORY AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => new
[patent_app_number] => 09/280703
[patent_app_country] => US
[patent_app_date] => 1999-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 4986
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0028/20020028545.pdf
[firstpage_image] =>[orig_patent_app_number] => 09280703
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/280703 | HIGHLY RESISTIVE STATIC RANDOM ACCESS MEMORY AND METHOD OF FABRICATING THE SAME | Mar 29, 1999 | Abandoned |
Array
(
[id] => 4351347
[patent_doc_number] => 06291363
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-18
[patent_title] => 'Surface treatment of DARC films to reduce defects in subsequent cap layers'
[patent_app_type] => 1
[patent_app_number] => 9/259713
[patent_app_country] => US
[patent_app_date] => 1999-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3407
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/291/06291363.pdf
[firstpage_image] =>[orig_patent_app_number] => 259713
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/259713 | Surface treatment of DARC films to reduce defects in subsequent cap layers | Feb 28, 1999 | Issued |
Array
(
[id] => 1462463
[patent_doc_number] => 06350643
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Reduced degradation of metal oxide ceramic due to diffusion of a mobile specie therefrom'
[patent_app_type] => B1
[patent_app_number] => 09/216370
[patent_app_country] => US
[patent_app_date] => 1998-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 9203
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/350/06350643.pdf
[firstpage_image] =>[orig_patent_app_number] => 09216370
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/216370 | Reduced degradation of metal oxide ceramic due to diffusion of a mobile specie therefrom | Dec 17, 1998 | Issued |
Array
(
[id] => 1409599
[patent_doc_number] => 06528389
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-04
[patent_title] => 'Substrate planarization with a chemical mechanical polishing stop layer'
[patent_app_type] => B1
[patent_app_number] => 09/213948
[patent_app_country] => US
[patent_app_date] => 1998-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 3413
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/528/06528389.pdf
[firstpage_image] =>[orig_patent_app_number] => 09213948
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/213948 | Substrate planarization with a chemical mechanical polishing stop layer | Dec 16, 1998 | Issued |
Array
(
[id] => 1040902
[patent_doc_number] => 06870201
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-22
[patent_title] => 'High voltage resistant edge structure for semiconductor components'
[patent_app_type] => utility
[patent_app_number] => 09/530553
[patent_app_country] => US
[patent_app_date] => 1998-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 4516
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/870/06870201.pdf
[firstpage_image] =>[orig_patent_app_number] => 09530553
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/530553 | High voltage resistant edge structure for semiconductor components | Nov 1, 1998 | Issued |
Array
(
[id] => 1602565
[patent_doc_number] => 06432744
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-13
[patent_title] => 'Wafer-scale assembly of chip-size packages'
[patent_app_type] => B1
[patent_app_number] => 09/183980
[patent_app_country] => US
[patent_app_date] => 1998-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 8830
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 20
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/432/06432744.pdf
[firstpage_image] =>[orig_patent_app_number] => 09183980
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/183980 | Wafer-scale assembly of chip-size packages | Oct 30, 1998 | Issued |
Array
(
[id] => 4343775
[patent_doc_number] => 06284587
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-04
[patent_title] => 'Fabricating method for semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/081567
[patent_app_country] => US
[patent_app_date] => 1998-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 41
[patent_no_of_words] => 11286
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/284/06284587.pdf
[firstpage_image] =>[orig_patent_app_number] => 081567
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/081567 | Fabricating method for semiconductor device | May 18, 1998 | Issued |
Array
(
[id] => 4286841
[patent_doc_number] => 06268262
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-31
[patent_title] => 'Method for forming air bridges'
[patent_app_type] => 1
[patent_app_number] => 8/999951
[patent_app_country] => US
[patent_app_date] => 1997-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 2221
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/268/06268262.pdf
[firstpage_image] =>[orig_patent_app_number] => 999951
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/999951 | Method for forming air bridges | Aug 10, 1997 | Issued |