Ismael Izaguirre
Examiner (ID: 255, Phone: (571)272-4987 , Office: P/3765 )
Most Active Art Unit | 3765 |
Art Unit(s) | 2899, 3741, 3732, 2407, 3765, 3742, 3408 |
Total Applications | 3433 |
Issued Applications | 2991 |
Pending Applications | 109 |
Abandoned Applications | 333 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 6882705
[patent_doc_number] => 20010049177
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-12-06
[patent_title] => 'Method for manufacturing semiconductor devices'
[patent_app_type] => new
[patent_app_number] => 09/872683
[patent_app_country] => US
[patent_app_date] => 2001-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 7653
[patent_no_of_claims] => 12
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[patent_words_short_claim] => 273
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0049/20010049177.pdf
[firstpage_image] =>[orig_patent_app_number] => 09872683
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/872683 | Method for manufacturing semiconductor devices | May 31, 2001 | Abandoned |
Array
(
[id] => 7014488
[patent_doc_number] => 20010051381
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-12-13
[patent_title] => 'Method for manufacturing a ferroelectric memory'
[patent_app_type] => new
[patent_app_number] => 09/867633
[patent_app_country] => US
[patent_app_date] => 2001-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1869
[patent_no_of_claims] => 13
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0051/20010051381.pdf
[firstpage_image] =>[orig_patent_app_number] => 09867633
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/867633 | Method for manufacturing a ferroelectric memory | May 30, 2001 | Abandoned |
Array
(
[id] => 1277876
[patent_doc_number] => 06645837
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-11
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 09/871033
[patent_app_country] => US
[patent_app_date] => 2001-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 4250
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[pdf_file] => patents/06/645/06645837.pdf
[firstpage_image] =>[orig_patent_app_number] => 09871033
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/871033 | Method of manufacturing semiconductor device | May 30, 2001 | Issued |
Array
(
[id] => 5801571
[patent_doc_number] => 20020009818
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-24
[patent_title] => 'Method of manufacturing a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 09/866743
[patent_app_country] => US
[patent_app_date] => 2001-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[patent_no_of_words] => 18231
[patent_no_of_claims] => 21
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0009/20020009818.pdf
[firstpage_image] =>[orig_patent_app_number] => 09866743
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/866743 | Method of manufacturing a semiconductor device | May 29, 2001 | Issued |
Array
(
[id] => 6893111
[patent_doc_number] => 20010015477
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-23
[patent_title] => 'Method of packaging fuses'
[patent_app_type] => new
[patent_app_number] => 09/844062
[patent_app_country] => US
[patent_app_date] => 2001-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 2186
[patent_no_of_claims] => 15
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0015/20010015477.pdf
[firstpage_image] =>[orig_patent_app_number] => 09844062
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/844062 | Method of packaging fuses | Apr 25, 2001 | Issued |
Array
(
[id] => 6130046
[patent_doc_number] => 20020076868
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-20
[patent_title] => 'MOS transistor in an integrated circuit and active area forming method'
[patent_app_type] => new
[patent_app_number] => 09/823274
[patent_app_country] => US
[patent_app_date] => 2001-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2773
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[pdf_file] => publications/A1/0076/20020076868.pdf
[firstpage_image] =>[orig_patent_app_number] => 09823274
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/823274 | MOS transistor in an integrated circuit and active area forming method | Mar 28, 2001 | Issued |
Array
(
[id] => 6900110
[patent_doc_number] => 20010009786
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-07-26
[patent_title] => 'Contact in semiconductor memory device and method of forming the same'
[patent_app_type] => new
[patent_app_number] => 09/814768
[patent_app_country] => US
[patent_app_date] => 2001-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 1906
[patent_no_of_claims] => 11
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0009/20010009786.pdf
[firstpage_image] =>[orig_patent_app_number] => 09814768
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/814768 | Contact in semiconductor memory device and method of forming the same | Mar 22, 2001 | Abandoned |
Array
(
[id] => 6908191
[patent_doc_number] => 20010010958
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-02
[patent_title] => 'FABRICATION METHOD TO APPROACH THE CONDUCTING STRUCTURE OF A DRAM CELL WITH STRAIGHT FORWARD BIT LINE'
[patent_app_type] => new
[patent_app_number] => 09/814431
[patent_app_country] => US
[patent_app_date] => 2001-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2546
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0010/20010010958.pdf
[firstpage_image] =>[orig_patent_app_number] => 09814431
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/814431 | FABRICATION METHOD TO APPROACH THE CONDUCTING STRUCTURE OF A DRAM CELL WITH STRAIGHT FORWARD BIT LINE | Mar 20, 2001 | Abandoned |
Array
(
[id] => 6900118
[patent_doc_number] => 20010009794
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-07-26
[patent_title] => 'Method and system for emitter partitioning for SiGe RF power transistors'
[patent_app_type] => new
[patent_app_number] => 09/801701
[patent_app_country] => US
[patent_app_date] => 2001-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2085
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[pdf_file] => publications/A1/0009/20010009794.pdf
[firstpage_image] =>[orig_patent_app_number] => 09801701
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/801701 | Method and system for emitter partitioning for SiGe RF power transistors | Mar 8, 2001 | Issued |
Array
(
[id] => 6900109
[patent_doc_number] => 20010009785
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-07-26
[patent_title] => 'Method of fabricating a supply decoupling capacitor'
[patent_app_type] => new
[patent_app_number] => 09/802201
[patent_app_country] => US
[patent_app_date] => 2001-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 6945
[patent_no_of_claims] => 15
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0009/20010009785.pdf
[firstpage_image] =>[orig_patent_app_number] => 09802201
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/802201 | Method of fabricating a supply decoupling capacitor | Mar 6, 2001 | Abandoned |
Array
(
[id] => 6900130
[patent_doc_number] => 20010009806
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-07-26
[patent_title] => 'Method for fabricating contact electrode of the semiconductor device'
[patent_app_type] => new
[patent_app_number] => 09/799521
[patent_app_country] => US
[patent_app_date] => 2001-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => publications/A1/0009/20010009806.pdf
[firstpage_image] =>[orig_patent_app_number] => 09799521
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/799521 | Method for fabricating contact electrode of the semiconductor device | Mar 6, 2001 | Abandoned |
Array
(
[id] => 1212830
[patent_doc_number] => 06709978
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-23
[patent_title] => 'Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer'
[patent_app_type] => B2
[patent_app_number] => 09/800373
[patent_app_country] => US
[patent_app_date] => 2001-03-06
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[firstpage_image] =>[orig_patent_app_number] => 09800373
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/800373 | Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer | Mar 5, 2001 | Issued |
Array
(
[id] => 6900126
[patent_doc_number] => 20010009802
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-07-26
[patent_title] => 'METHOD OF FORMING INTEGRATED BONDING PADS INCLUDING CLOSED VIAS AND CLOSED CONDUCTIVE PATTERNS'
[patent_app_type] => new
[patent_app_number] => 09/800138
[patent_app_country] => US
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[pdf_file] => publications/A1/0009/20010009802.pdf
[firstpage_image] =>[orig_patent_app_number] => 09800138
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/800138 | METHOD OF FORMING INTEGRATED BONDING PADS INCLUDING CLOSED VIAS AND CLOSED CONDUCTIVE PATTERNS | Mar 5, 2001 | Abandoned |
Array
(
[id] => 1587969
[patent_doc_number] => 06359343
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-19
[patent_title] => 'Temperature stabilization in flip chip technology'
[patent_app_type] => B1
[patent_app_number] => 09/799446
[patent_app_country] => US
[patent_app_date] => 2001-03-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/359/06359343.pdf
[firstpage_image] =>[orig_patent_app_number] => 09799446
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/799446 | Temperature stabilization in flip chip technology | Mar 4, 2001 | Issued |
Array
(
[id] => 1500414
[patent_doc_number] => 06486056
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-11-26
[patent_title] => 'Process for making integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level'
[patent_app_type] => B2
[patent_app_number] => 09/790821
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/790821 | Process for making integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level | Feb 21, 2001 | Issued |
Array
(
[id] => 6887801
[patent_doc_number] => 20010008795
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-07-19
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => new-utility
[patent_app_number] => 09/789764
[patent_app_country] => US
[patent_app_date] => 2001-02-22
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09789764
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/789764 | Semiconductor device and method for manufacturing the same | Feb 21, 2001 | Issued |
Array
(
[id] => 7040035
[patent_doc_number] => 20010005038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-06-28
[patent_title] => 'Integrated circuit chip and method for fabricating the same'
[patent_app_type] => new-utility
[patent_app_number] => 09/791082
[patent_app_country] => US
[patent_app_date] => 2001-02-22
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/791082 | Integrated circuit chip and method for fabricating the same | Feb 21, 2001 | Abandoned |
Array
(
[id] => 1545227
[patent_doc_number] => 06444539
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-03
[patent_title] => 'Method for producing a shallow trench isolation filled with thermal oxide'
[patent_app_type] => B1
[patent_app_number] => 09/784892
[patent_app_country] => US
[patent_app_date] => 2001-02-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/784892 | Method for producing a shallow trench isolation filled with thermal oxide | Feb 14, 2001 | Issued |
Array
(
[id] => 6899491
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[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-07-26
[patent_title] => 'Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth through offset masks'
[patent_app_type] => new
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[patent_app_country] => US
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Array
(
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[patent_app_type] => new
[patent_app_number] => 09/780071
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/780071 | Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth through offset masks | Feb 8, 2001 | Abandoned |