Search

Ismael Izaguirre

Examiner (ID: 255, Phone: (571)272-4987 , Office: P/3765 )

Most Active Art Unit
3765
Art Unit(s)
2899, 3741, 3732, 2407, 3765, 3742, 3408
Total Applications
3433
Issued Applications
2991
Pending Applications
109
Abandoned Applications
333

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6875370 [patent_doc_number] => 20010000114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-04-05 [patent_title] => 'Semiconductor device with wiring layer of low resistance' [patent_app_type] => new-utility [patent_app_number] => 09/730562 [patent_app_country] => US [patent_app_date] => 2000-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4614 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000114.pdf [firstpage_image] =>[orig_patent_app_number] => 09730562 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/730562
Semiconductor device with wiring layer of low resistance Dec 6, 2000 Abandoned
Array ( [id] => 1095857 [patent_doc_number] => 06821814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method for joining a semiconductor chip to a chip carrier substrate and resulting chip package' [patent_app_type] => B2 [patent_app_number] => 09/731341 [patent_app_country] => US [patent_app_date] => 2000-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6230 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821814.pdf [firstpage_image] =>[orig_patent_app_number] => 09731341 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/731341
Method for joining a semiconductor chip to a chip carrier substrate and resulting chip package Dec 5, 2000 Issued
Array ( [id] => 1585448 [patent_doc_number] => 06358799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-03-19 [patent_title] => 'Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device' [patent_app_type] => B2 [patent_app_number] => 09/727536 [patent_app_country] => US [patent_app_date] => 2000-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 51 [patent_no_of_words] => 17577 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358799.pdf [firstpage_image] =>[orig_patent_app_number] => 09727536 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/727536
Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device Dec 3, 2000 Issued
Array ( [id] => 1408969 [patent_doc_number] => 06528353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-04 [patent_title] => 'Chip stack-type semiconductor package and method for fabricating the same' [patent_app_type] => B2 [patent_app_number] => 09/727778 [patent_app_country] => US [patent_app_date] => 2000-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 3835 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528353.pdf [firstpage_image] =>[orig_patent_app_number] => 09727778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/727778
Chip stack-type semiconductor package and method for fabricating the same Dec 3, 2000 Issued
Array ( [id] => 6902010 [patent_doc_number] => 20010000919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-10 [patent_title] => 'MOS-gated power device having extended trench and doping zone and process for forming same' [patent_app_type] => new-utility [patent_app_number] => 09/726682 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2053 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000919.pdf [firstpage_image] =>[orig_patent_app_number] => 09726682 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/726682
MOS-gated power device having extended trench and doping zone and process for forming same Nov 29, 2000 Abandoned
Array ( [id] => 6893090 [patent_doc_number] => 20010015456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Method of forming a composite interpoly gate dielectric' [patent_app_type] => new [patent_app_number] => 09/725843 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2869 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20010015456.pdf [firstpage_image] =>[orig_patent_app_number] => 09725843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/725843
Method of forming a composite interpoly gate dielectric Nov 29, 2000 Issued
Array ( [id] => 4328866 [patent_doc_number] => 06312986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Concentric container fin capacitor and method' [patent_app_type] => 1 [patent_app_number] => 9/715001 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 3425 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/312/06312986.pdf [firstpage_image] =>[orig_patent_app_number] => 715001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/715001
Concentric container fin capacitor and method Nov 19, 2000 Issued
Array ( [id] => 1459295 [patent_doc_number] => 06391696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Field effect transistor and method of manufacturing thereof' [patent_app_type] => B1 [patent_app_number] => 09/714521 [patent_app_country] => US [patent_app_date] => 2000-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 5616 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391696.pdf [firstpage_image] =>[orig_patent_app_number] => 09714521 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/714521
Field effect transistor and method of manufacturing thereof Nov 16, 2000 Issued
Array ( [id] => 1485117 [patent_doc_number] => 06365436 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Connecting multiple microelectronic elements with lead deformation' [patent_app_type] => B1 [patent_app_number] => 09/712631 [patent_app_country] => US [patent_app_date] => 2000-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 10857 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365436.pdf [firstpage_image] =>[orig_patent_app_number] => 09712631 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/712631
Connecting multiple microelectronic elements with lead deformation Nov 13, 2000 Issued
09/707991 Method of forming a three-dimensional polysilicon layer on a semiconductor wafer Nov 7, 2000 Abandoned
09/705692 Semiconductor device and process for producing the semiconductor device Nov 5, 2000 Abandoned
Array ( [id] => 1050013 [patent_doc_number] => 06861290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-01 [patent_title] => 'Flip-chip adaptor package for bare die' [patent_app_type] => utility [patent_app_number] => 09/699537 [patent_app_country] => US [patent_app_date] => 2000-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2930 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/861/06861290.pdf [firstpage_image] =>[orig_patent_app_number] => 09699537 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/699537
Flip-chip adaptor package for bare die Oct 29, 2000 Issued
Array ( [id] => 1561125 [patent_doc_number] => 06362058 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Method for controlling an implant profile in the channel of a transistor' [patent_app_type] => B1 [patent_app_number] => 09/697922 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 4907 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362058.pdf [firstpage_image] =>[orig_patent_app_number] => 09697922 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/697922
Method for controlling an implant profile in the channel of a transistor Oct 25, 2000 Issued
Array ( [id] => 1315261 [patent_doc_number] => 06607928 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Integrated circuit device having an embedded heat slug' [patent_app_type] => B1 [patent_app_number] => 09/676268 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2091 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/607/06607928.pdf [firstpage_image] =>[orig_patent_app_number] => 09676268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/676268
Integrated circuit device having an embedded heat slug Sep 27, 2000 Issued
Array ( [id] => 1578039 [patent_doc_number] => 06448119 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Field effect transistor and method of fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/667231 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 7705 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448119.pdf [firstpage_image] =>[orig_patent_app_number] => 09667231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/667231
Field effect transistor and method of fabricating the same Sep 21, 2000 Issued
09/665062 Resin-encapsulated semiconductor apparatus and process for its fabrication Sep 18, 2000 Abandoned
Array ( [id] => 1367477 [patent_doc_number] => 06566234 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Semiconductor flip-chip package and method for the fabrication thereof' [patent_app_type] => B1 [patent_app_number] => 09/662642 [patent_app_country] => US [patent_app_date] => 2000-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 11095 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566234.pdf [firstpage_image] =>[orig_patent_app_number] => 09662642 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/662642
Semiconductor flip-chip package and method for the fabrication thereof Sep 14, 2000 Issued
Array ( [id] => 1550261 [patent_doc_number] => 06399430 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Field effect transistor and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/656267 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 4416 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399430.pdf [firstpage_image] =>[orig_patent_app_number] => 09656267 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/656267
Field effect transistor and method of manufacturing the same Sep 5, 2000 Issued
Array ( [id] => 4407633 [patent_doc_number] => 06239021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Dual barrier and conductor deposition in a dual damascene process for semiconductors' [patent_app_type] => 1 [patent_app_number] => 9/655110 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2743 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239021.pdf [firstpage_image] =>[orig_patent_app_number] => 655110 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/655110
Dual barrier and conductor deposition in a dual damascene process for semiconductors Sep 4, 2000 Issued
Array ( [id] => 1080492 [patent_doc_number] => 06835650 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-28 [patent_title] => 'ESD/EOS protection structure for integrated circuit devices and methods of fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/640237 [patent_app_country] => US [patent_app_date] => 2000-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 40 [patent_no_of_words] => 5089 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 547 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/835/06835650.pdf [firstpage_image] =>[orig_patent_app_number] => 09640237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/640237
ESD/EOS protection structure for integrated circuit devices and methods of fabricating the same Aug 15, 2000 Issued
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