
Ismail A. Muse
Examiner (ID: 4864, Phone: (571)272-1470 , Office: P/2819 )
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2819, 2812, 2829 |
| Total Applications | 722 |
| Issued Applications | 581 |
| Pending Applications | 84 |
| Abandoned Applications | 83 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12047567
[patent_doc_number] => 09825177
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-21
[patent_title] => 'Manufacturing method of a semiconductor device using multiple etching mask'
[patent_app_type] => utility
[patent_app_number] => 15/217080
[patent_app_country] => US
[patent_app_date] => 2016-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 46
[patent_figures_cnt] => 112
[patent_no_of_words] => 43126
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15217080
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/217080 | Manufacturing method of a semiconductor device using multiple etching mask | Jul 21, 2016 | Issued |
Array
(
[id] => 12457413
[patent_doc_number] => 09985009
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-29
[patent_title] => Manufacturing method of LED light emitting device
[patent_app_type] => utility
[patent_app_number] => 15/216983
[patent_app_country] => US
[patent_app_date] => 2016-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 25
[patent_no_of_words] => 8181
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 393
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15216983
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/216983 | Manufacturing method of LED light emitting device | Jul 21, 2016 | Issued |
Array
(
[id] => 11730886
[patent_doc_number] => 20170192328
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-06
[patent_title] => 'DISPLAY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/217625
[patent_app_country] => US
[patent_app_date] => 2016-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 12492
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15217625
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/217625 | Display device with pixel arrangemnt for high resolution | Jul 21, 2016 | Issued |
Array
(
[id] => 14058211
[patent_doc_number] => 10233389
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-19
[patent_title] => Semiconductor nanoparticles and method of producing semiconductor nanoparticles
[patent_app_type] => utility
[patent_app_number] => 15/215961
[patent_app_country] => US
[patent_app_date] => 2016-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 12574
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15215961
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/215961 | Semiconductor nanoparticles and method of producing semiconductor nanoparticles | Jul 20, 2016 | Issued |
Array
(
[id] => 11110908
[patent_doc_number] => 20160307878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-20
[patent_title] => 'RECONSTITUTED WAFER-LEVEL PACKAGE DRAM'
[patent_app_type] => utility
[patent_app_number] => 15/196635
[patent_app_country] => US
[patent_app_date] => 2016-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7631
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15196635
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/196635 | Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package | Jun 28, 2016 | Issued |
Array
(
[id] => 15388747
[patent_doc_number] => 10535572
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-14
[patent_title] => Device arrangement structure assembly and test method
[patent_app_type] => utility
[patent_app_number] => 15/193542
[patent_app_country] => US
[patent_app_date] => 2016-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4172
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193542
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/193542 | Device arrangement structure assembly and test method | Jun 26, 2016 | Issued |
Array
(
[id] => 12047361
[patent_doc_number] => 09824970
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-11-21
[patent_title] => 'Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structures'
[patent_app_type] => utility
[patent_app_number] => 15/193300
[patent_app_country] => US
[patent_app_date] => 2016-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 26
[patent_no_of_words] => 8467
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 258
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193300
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/193300 | Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structures | Jun 26, 2016 | Issued |
Array
(
[id] => 13660975
[patent_doc_number] => 10160639
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-25
[patent_title] => Semiconductor structure for MEMS Device
[patent_app_type] => utility
[patent_app_number] => 15/193410
[patent_app_country] => US
[patent_app_date] => 2016-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 5593
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193410
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/193410 | Semiconductor structure for MEMS Device | Jun 26, 2016 | Issued |
Array
(
[id] => 12102289
[patent_doc_number] => 09859389
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-01-02
[patent_title] => 'Sidewall protective layer for contact formation'
[patent_app_type] => utility
[patent_app_number] => 15/193404
[patent_app_country] => US
[patent_app_date] => 2016-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 5061
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193404
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/193404 | Sidewall protective layer for contact formation | Jun 26, 2016 | Issued |
Array
(
[id] => 13724437
[patent_doc_number] => 20170373174
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-28
[patent_title] => RADIATION ENHANCED BIPOLAR TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 15/193015
[patent_app_country] => US
[patent_app_date] => 2016-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4761
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193015
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/193015 | Radiation enhanced bipolar transistor | Jun 24, 2016 | Issued |
Array
(
[id] => 13755313
[patent_doc_number] => 10170611
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-01-01
[patent_title] => T-gate field effect transistor with non-linear channel layer and/or gate foot face
[patent_app_type] => utility
[patent_app_number] => 15/192942
[patent_app_country] => US
[patent_app_date] => 2016-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 32
[patent_no_of_words] => 10959
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192942
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/192942 | T-gate field effect transistor with non-linear channel layer and/or gate foot face | Jun 23, 2016 | Issued |
Array
(
[id] => 15476515
[patent_doc_number] => 10554153
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-04
[patent_title] => MEMS device for harvesting sound energy and methods for fabricating same
[patent_app_type] => utility
[patent_app_number] => 15/185642
[patent_app_country] => US
[patent_app_date] => 2016-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 17
[patent_no_of_words] => 4301
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15185642
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/185642 | MEMS device for harvesting sound energy and methods for fabricating same | Jun 16, 2016 | Issued |
Array
(
[id] => 11883636
[patent_doc_number] => 09754817
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-09-05
[patent_title] => 'Semiconductor structures having an insulative island structure'
[patent_app_type] => utility
[patent_app_number] => 15/170043
[patent_app_country] => US
[patent_app_date] => 2016-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 22
[patent_no_of_words] => 7781
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170043
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/170043 | Semiconductor structures having an insulative island structure | May 31, 2016 | Issued |
Array
(
[id] => 11817888
[patent_doc_number] => 09721846
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-08-01
[patent_title] => 'Hybrid integration fabrication of nanowire gate-all-around GE PFET and polygonal III-V PFET CMOS device'
[patent_app_type] => utility
[patent_app_number] => 15/157421
[patent_app_country] => US
[patent_app_date] => 2016-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 3464
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15157421
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/157421 | Hybrid integration fabrication of nanowire gate-all-around GE PFET and polygonal III-V PFET CMOS device | May 17, 2016 | Issued |
Array
(
[id] => 13257493
[patent_doc_number] => 10141444
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-11-27
[patent_title] => Oxide thin-film transistor with illuminated OHMIC contact layers, array substrate and methods for manufacturing the same, and display device
[patent_app_type] => utility
[patent_app_number] => 15/156858
[patent_app_country] => US
[patent_app_date] => 2016-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 4963
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 286
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15156858
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/156858 | Oxide thin-film transistor with illuminated OHMIC contact layers, array substrate and methods for manufacturing the same, and display device | May 16, 2016 | Issued |
Array
(
[id] => 11740286
[patent_doc_number] => 09704879
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-11
[patent_title] => 'Integrated circuitry components, switches, and memory cells'
[patent_app_type] => utility
[patent_app_number] => 15/155289
[patent_app_country] => US
[patent_app_date] => 2016-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 15
[patent_no_of_words] => 7730
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15155289
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/155289 | Integrated circuitry components, switches, and memory cells | May 15, 2016 | Issued |
Array
(
[id] => 12019778
[patent_doc_number] => 09812489
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-07
[patent_title] => 'Pixels with photodiodes formed from epitaxial silicon'
[patent_app_type] => utility
[patent_app_number] => 15/133129
[patent_app_country] => US
[patent_app_date] => 2016-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 22
[patent_no_of_words] => 6038
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15133129
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/133129 | Pixels with photodiodes formed from epitaxial silicon | Apr 18, 2016 | Issued |
Array
(
[id] => 13682737
[patent_doc_number] => 20160380105
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-12-29
[patent_title] => OXIDE THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/131644
[patent_app_country] => US
[patent_app_date] => 2016-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5031
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15131644
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/131644 | OXIDE THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE | Apr 17, 2016 | Abandoned |
Array
(
[id] => 11028800
[patent_doc_number] => 20160225756
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-08-04
[patent_title] => 'METHOD OF FORMING AN ESD DEVICE AND STRUCTURE THEREFOR'
[patent_app_type] => utility
[patent_app_number] => 15/094853
[patent_app_country] => US
[patent_app_date] => 2016-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 10479
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 15
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15094853
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/094853 | ESD device and structure therefor | Apr 7, 2016 | Issued |
Array
(
[id] => 12102238
[patent_doc_number] => 09859338
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-02
[patent_title] => 'Three-dimensional resistive memory'
[patent_app_type] => utility
[patent_app_number] => 15/075215
[patent_app_country] => US
[patent_app_date] => 2016-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 5795
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15075215
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/075215 | Three-dimensional resistive memory | Mar 20, 2016 | Issued |