Search

J Casimer Jacyna

Examiner (ID: 9615, Phone: (469)295-9095 , Office: P/3754 )

Most Active Art Unit
3754
Art Unit(s)
3105, 3754, 2899, 2403, 3751
Total Applications
3773
Issued Applications
2794
Pending Applications
239
Abandoned Applications
673

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18772781 [patent_doc_number] => 20230367607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => METHODS AND APPARATUS FOR HYPERVISOR BOOT UP [patent_app_type] => utility [patent_app_number] => 18/360723 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360723 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360723
METHODS AND APPARATUS FOR HYPERVISOR BOOT UP Jul 26, 2023 Pending
Array ( [id] => 18742039 [patent_doc_number] => 20230351021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => Secure In-Service Firmware Update [patent_app_type] => utility [patent_app_number] => 18/349147 [patent_app_country] => US [patent_app_date] => 2023-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349147 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/349147
Secure In-Service Firmware Update Jul 8, 2023 Pending
Array ( [id] => 18440843 [patent_doc_number] => 20230188139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => ULTRA-LOW POWER ADAPTIVELY RECONFIGURABLE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/082900 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18082900 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/082900
ULTRA-LOW POWER ADAPTIVELY RECONFIGURABLE SYSTEM Dec 15, 2022 Pending
Array ( [id] => 18320315 [patent_doc_number] => 20230118443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => Profiling User Activity To Achieve Social And Governance Objectives [patent_app_type] => utility [patent_app_number] => 17/936992 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 42679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17936992 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/936992
Profiling User Activity To Achieve Social And Governance Objectives Sep 29, 2022 Pending
Array ( [id] => 18727600 [patent_doc_number] => 20230341891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => GLITCH-FREE CLOCK SWITCHING CIRCUIT WITH CLOCK LOSS TOLERANCE AND OPERATION METHOD THEREOF AND GLITCH-FREE CLOCK SWITCHING DEVICE [patent_app_type] => utility [patent_app_number] => 17/896084 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896084 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/896084
GLITCH-FREE CLOCK SWITCHING CIRCUIT WITH CLOCK LOSS TOLERANCE AND OPERATION METHOD THEREOF AND GLITCH-FREE CLOCK SWITCHING DEVICE Aug 25, 2022 Pending
Array ( [id] => 18819304 [patent_doc_number] => 20230393644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => VOLTAGE FREQUENCY SCALING BASED ON ERROR RATE [patent_app_type] => utility [patent_app_number] => 17/893850 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893850 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893850
VOLTAGE FREQUENCY SCALING BASED ON ERROR RATE Aug 22, 2022 Pending
Array ( [id] => 18976242 [patent_doc_number] => 20240056334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => METHODS AND APPARATUS FOR DIGITAL DATA COMMUNICATION WITH BUS POWER OVER INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 17/885339 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885339 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/885339
METHODS AND APPARATUS FOR DIGITAL DATA COMMUNICATION WITH BUS POWER OVER INTERCONNECTS Aug 9, 2022 Pending
Array ( [id] => 18925554 [patent_doc_number] => 20240028558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => DISABLING PROCESSOR CORES FOR BEST LATENCY IN A MULTIPLE CORE PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/871034 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871034 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/871034
DISABLING PROCESSOR CORES FOR BEST LATENCY IN A MULTIPLE CORE PROCESSOR Jul 21, 2022 Pending
Array ( [id] => 18925732 [patent_doc_number] => 20240028736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => VALIDATION AND RECOVERY OF OPERATING SYSTEM BOOT FILES DURING OS INSTALLATION AND RUNTIME FOR UEFI SECURE BOOT SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/870979 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870979 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/870979
VALIDATION AND RECOVERY OF OPERATING SYSTEM BOOT FILES DURING OS INSTALLATION AND RUNTIME FOR UEFI SECURE BOOT SYSTEMS Jul 21, 2022 Pending
Array ( [id] => 17961894 [patent_doc_number] => 20220342475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => TERMINAL CONTROL METHOD AND TERMINAL [patent_app_type] => utility [patent_app_number] => 17/861997 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861997 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/861997
TERMINAL CONTROL METHOD AND TERMINAL Jul 10, 2022 Abandoned
Array ( [id] => 18881084 [patent_doc_number] => 20240004453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => TECHNIQUES FOR REDUCING PROCESSOR POWER CONSUMPTION [patent_app_type] => utility [patent_app_number] => 17/854858 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854858 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854858
TECHNIQUES FOR REDUCING PROCESSOR POWER CONSUMPTION Jun 29, 2022 Pending
Array ( [id] => 18546791 [patent_doc_number] => 11720140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Device clock setting while booting a device [patent_app_type] => utility [patent_app_number] => 17/809301 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4599 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809301 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809301
Device clock setting while booting a device Jun 27, 2022 Issued
Array ( [id] => 17931839 [patent_doc_number] => 20220326964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => PROCESSOR FOR INITIALIZING MODEL FILE OF APPLICATION AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/809485 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809485 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809485
PROCESSOR FOR INITIALIZING MODEL FILE OF APPLICATION AND ELECTRONIC DEVICE INCLUDING THE SAME Jun 27, 2022 Pending
Array ( [id] => 18059916 [patent_doc_number] => 20220391002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => PREDICTIVE POWER MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/842517 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842517 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842517
PREDICTIVE POWER MANAGEMENT Jun 15, 2022 Pending
Array ( [id] => 18038347 [patent_doc_number] => 20220382563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => PROGRAM STARTUP METHOD, ELECTRONIC SYSTEM, AND NON-TRANSITORY STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/829247 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829247 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/829247
PROGRAM STARTUP METHOD, ELECTRONIC SYSTEM, AND NON-TRANSITORY STORAGE MEDIUM May 30, 2022 Pending
Array ( [id] => 17991751 [patent_doc_number] => 20220357788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => PREDICTIVE POWER MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/826895 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826895 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826895
PREDICTIVE POWER MANAGEMENT May 26, 2022 Pending
Array ( [id] => 18022746 [patent_doc_number] => 20220374245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => PERSONALIZED AVATAR EXPERIENCE DURING A SYSTEM BOOT PROCESS [patent_app_type] => utility [patent_app_number] => 17/664107 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664107 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664107
PERSONALIZED AVATAR EXPERIENCE DURING A SYSTEM BOOT PROCESS May 18, 2022 Pending
Array ( [id] => 17794027 [patent_doc_number] => 20220253119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => MULTI-DIE STACKS WITH POWER MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/732792 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732792 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/732792
Multi-die stacks with power management Apr 28, 2022 Issued
Array ( [id] => 18728182 [patent_doc_number] => 20230342475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => SMART NETWORK INTERFACE CONTROLLER SIGNATURE DATABASE EMULATION [patent_app_type] => utility [patent_app_number] => 17/728636 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17728636 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/728636
SMART NETWORK INTERFACE CONTROLLER SIGNATURE DATABASE EMULATION Apr 24, 2022 Pending
Array ( [id] => 18630553 [patent_doc_number] => 20230289446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => SECURE MULTI-BIOS-IMAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 17/690164 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690164 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/690164
SECURE MULTI-BIOS-IMAGE SYSTEM Mar 8, 2022 Pending
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