Search

J. Foss

Examiner (ID: 17159)

Most Active Art Unit
3505
Art Unit(s)
3505, 1506, 3502
Total Applications
1479
Issued Applications
1438
Pending Applications
2
Abandoned Applications
39

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16314746 [patent_doc_number] => 20200293484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => SERIAL PERIPHERAL INTERFACE MASTER [patent_app_type] => utility [patent_app_number] => 16/799839 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799839 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/799839
Serial peripheral interface master Feb 24, 2020 Issued
Array ( [id] => 17061873 [patent_doc_number] => 11106474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => System, method, and apparatus for DVSEC for efficient peripheral management [patent_app_type] => utility [patent_app_number] => 16/773500 [patent_app_country] => US [patent_app_date] => 2020-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 23794 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16773500 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/773500
System, method, and apparatus for DVSEC for efficient peripheral management Jan 26, 2020 Issued
Array ( [id] => 18291305 [patent_doc_number] => 11620175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Method and apparatus for disconnecting link between PCIe device and host [patent_app_type] => utility [patent_app_number] => 16/740717 [patent_app_country] => US [patent_app_date] => 2020-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16740717 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/740717
Method and apparatus for disconnecting link between PCIe device and host Jan 12, 2020 Issued
Array ( [id] => 16848738 [patent_doc_number] => 20210149483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => SELECTIVE IMAGE CAPTURE BASED ON MULTI-MODAL SENSOR INPUT [patent_app_type] => utility [patent_app_number] => 16/686403 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16686403 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/686403
SELECTIVE IMAGE CAPTURE BASED ON MULTI-MODAL SENSOR INPUT Nov 17, 2019 Abandoned
Array ( [id] => 16849089 [patent_doc_number] => 20210149834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => System-In-Package Architecture with Wireless Bus Interconnect [patent_app_type] => utility [patent_app_number] => 16/685090 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685090 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685090
System-in-package architecture with wireless bus interconnect Nov 14, 2019 Issued
Array ( [id] => 17209569 [patent_doc_number] => 11169942 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-09 [patent_title] => Double data rate (DDR) radio frequency (RF) digitization module for software-defined radio (SDR) [patent_app_type] => utility [patent_app_number] => 16/681466 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2351 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681466 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681466
Double data rate (DDR) radio frequency (RF) digitization module for software-defined radio (SDR) Nov 11, 2019 Issued
Array ( [id] => 17209572 [patent_doc_number] => 11169945 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-09 [patent_title] => Bridge supporting multiple interfaces access to subsystem [patent_app_type] => utility [patent_app_number] => 16/675997 [patent_app_country] => US [patent_app_date] => 2019-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3787 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16675997 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/675997
Bridge supporting multiple interfaces access to subsystem Nov 5, 2019 Issued
Array ( [id] => 16810579 [patent_doc_number] => 20210133134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => Sequentiality Characterization of Input/Output Workloads [patent_app_type] => utility [patent_app_number] => 16/671617 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671617 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671617
Sequentiality characterization of input/output workloads Oct 31, 2019 Issued
Array ( [id] => 16402093 [patent_doc_number] => 20200342951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => SYSTEM FOR DETECTING COMPUTER STARTUP AND METHOD OF SYSTEM [patent_app_type] => utility [patent_app_number] => 16/662199 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16662199 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/662199
System for detecting computer startup and method of system Oct 23, 2019 Issued
Array ( [id] => 17744339 [patent_doc_number] => 11392406 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-19 [patent_title] => Alternative interrupt reporting channels for microcontroller access devices [patent_app_type] => utility [patent_app_number] => 16/660716 [patent_app_country] => US [patent_app_date] => 2019-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16660716 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/660716
Alternative interrupt reporting channels for microcontroller access devices Oct 21, 2019 Issued
Array ( [id] => 16338229 [patent_doc_number] => 10789186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Apparatuses and methods including memory commands for semiconductor memories [patent_app_type] => utility [patent_app_number] => 16/657474 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 15649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657474 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/657474
Apparatuses and methods including memory commands for semiconductor memories Oct 17, 2019 Issued
Array ( [id] => 15152035 [patent_doc_number] => 20190354495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => INTEGRATED CIRCUIT HAVING LANES INTERCHANGEABLE BETWEEN CLOCK AND DATA LANES IN CLOCK FORWARD INTERFACE RECEIVER [patent_app_type] => utility [patent_app_number] => 16/529575 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16529575 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/529575
Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver Jul 31, 2019 Issued
Array ( [id] => 15152033 [patent_doc_number] => 20190354494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => Sending Data From an Arrangement of Processor Modules [patent_app_type] => utility [patent_app_number] => 16/525833 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16525833 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/525833
Sending data from an arrangement of processor modules Jul 29, 2019 Issued
Array ( [id] => 17682422 [patent_doc_number] => 11366675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Systems and devices for accessing a state machine [patent_app_type] => utility [patent_app_number] => 16/525187 [patent_app_country] => US [patent_app_date] => 2019-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 17050 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16525187 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/525187
Systems and devices for accessing a state machine Jul 28, 2019 Issued
Array ( [id] => 16537040 [patent_doc_number] => 10879660 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-29 [patent_title] => Asymmetric high-speed interconnect routing interposer [patent_app_type] => utility [patent_app_number] => 16/523091 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4298 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523091 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523091
Asymmetric high-speed interconnect routing interposer Jul 25, 2019 Issued
Array ( [id] => 16478336 [patent_doc_number] => 10853284 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-01 [patent_title] => Supporting PCI-e message-signaled interrupts in computer system with shared peripheral interrupts [patent_app_type] => utility [patent_app_number] => 16/518818 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16518818 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/518818
Supporting PCI-e message-signaled interrupts in computer system with shared peripheral interrupts Jul 21, 2019 Issued
Array ( [id] => 15412697 [patent_doc_number] => 20200026671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => CIRCUITRY SYSTEM AND METHOD FOR PROCESSING INTERRUPT PRIORITY [patent_app_type] => utility [patent_app_number] => 16/515689 [patent_app_country] => US [patent_app_date] => 2019-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16515689 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/515689
CIRCUITRY SYSTEM AND METHOD FOR PROCESSING INTERRUPT PRIORITY Jul 17, 2019 Abandoned
Array ( [id] => 15198159 [patent_doc_number] => 10496575 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-03 [patent_title] => Multi-protocol determining method based on CAN bus [patent_app_type] => utility [patent_app_number] => 16/439688 [patent_app_country] => US [patent_app_date] => 2019-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3045 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16439688 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/439688
Multi-protocol determining method based on CAN bus Jun 11, 2019 Issued
Array ( [id] => 17682523 [patent_doc_number] => 11366777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Process control device having modern architecture and legacy compatibility [patent_app_type] => utility [patent_app_number] => 16/438252 [patent_app_country] => US [patent_app_date] => 2019-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7313 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16438252 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/438252
Process control device having modern architecture and legacy compatibility Jun 10, 2019 Issued
Array ( [id] => 16496646 [patent_doc_number] => 10862704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Time-based secure access control system [patent_app_type] => utility [patent_app_number] => 16/438402 [patent_app_country] => US [patent_app_date] => 2019-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3313 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16438402 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/438402
Time-based secure access control system Jun 10, 2019 Issued
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