Search

J. Reed Fisher

Examiner (ID: 6827)

Most Active Art Unit
3307
Art Unit(s)
3103, 2854, 3307
Total Applications
1305
Issued Applications
1002
Pending Applications
12
Abandoned Applications
291

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18983725 [patent_doc_number] => 11908915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Method of manufacturing semiconductor devices and semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/751328 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 42 [patent_no_of_words] => 12062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751328 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751328
Method of manufacturing semiconductor devices and semiconductor devices May 22, 2022 Issued
Array ( [id] => 19844115 [patent_doc_number] => 12256530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Method of manufacturing semiconductor structure, semiconductor structure and memory [patent_app_type] => utility [patent_app_number] => 17/663871 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 9188 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663871 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/663871
Method of manufacturing semiconductor structure, semiconductor structure and memory May 17, 2022 Issued
Array ( [id] => 17833713 [patent_doc_number] => 20220271017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => HIGH DENSITY PIXELATED LED AND DEVICES AND METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/740982 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17740982 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/740982
High density pixelated LED and devices and methods thereof May 9, 2022 Issued
Array ( [id] => 19796241 [patent_doc_number] => 12237210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/740095 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 40 [patent_no_of_words] => 13266 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17740095 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/740095
Semiconductor device May 8, 2022 Issued
Array ( [id] => 18142537 [patent_doc_number] => 20230016381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => Metal Capping Layer for Reducing Gate Resistance in Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 17/738238 [patent_app_country] => US [patent_app_date] => 2022-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17738238 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/738238
Metal capping layer for reducing gate resistance in semiconductor devices May 5, 2022 Issued
Array ( [id] => 18840299 [patent_doc_number] => 11848382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/734686 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8972 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734686 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/734686
Semiconductor device May 1, 2022 Issued
Array ( [id] => 17811088 [patent_doc_number] => 20220262923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => SACRIFICIAL FIN FOR CONTACT SELF-ALIGNMENT [patent_app_type] => utility [patent_app_number] => 17/728437 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17728437 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/728437
Sacrificial fin for contact self-alignment Apr 24, 2022 Issued
Array ( [id] => 18983730 [patent_doc_number] => 11908920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Fin field-effect transistor device and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/722787 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 59 [patent_no_of_words] => 11959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722787
Fin field-effect transistor device and method of forming the same Apr 17, 2022 Issued
Array ( [id] => 17764905 [patent_doc_number] => 20220238518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/659069 [patent_app_country] => US [patent_app_date] => 2022-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17659069 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/659069
Semiconductor device and method of fabricating the same Apr 12, 2022 Issued
Array ( [id] => 18680060 [patent_doc_number] => 20230317718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => JUNCTION FIELD EFFECT TRANSISTORS FOR LOW VOLTAGE AND LOW TEMPERATURE OPERATION [patent_app_type] => utility [patent_app_number] => 17/711854 [patent_app_country] => US [patent_app_date] => 2022-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17711854 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/711854
Junction field effect transistors for low voltage and low temperature operation Mar 31, 2022 Issued
Array ( [id] => 18680192 [patent_doc_number] => 20230317850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => NON-EPITAXIAL ELECTRICAL COUPLING BETWEEN A FRONT SIDE TRENCH CONNECTOR AND BACK SIDE CONTACTS OF A TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/710857 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710857 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/710857
NON-EPITAXIAL ELECTRICAL COUPLING BETWEEN A FRONT SIDE TRENCH CONNECTOR AND BACK SIDE CONTACTS OF A TRANSISTOR Mar 30, 2022 Pending
Array ( [id] => 18679936 [patent_doc_number] => 20230317594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => DEVICE PERFORMANCE TUNING BY DEEP TRENCH VIA (DVB) PROXIMITY EFFECT IN ARCHITECTURE OF BACKSIDE POWER DELIVERY [patent_app_type] => utility [patent_app_number] => 17/710802 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/710802
DEVICE PERFORMANCE TUNING BY DEEP TRENCH VIA (DVB) PROXIMITY EFFECT IN ARCHITECTURE OF BACKSIDE POWER DELIVERY Mar 30, 2022 Pending
Array ( [id] => 20230420 [patent_doc_number] => 12419085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Integrated circuit structures having backside gate tie-down [patent_app_type] => utility [patent_app_number] => 17/709374 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 36 [patent_no_of_words] => 12778 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709374 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/709374
Integrated circuit structures having backside gate tie-down Mar 29, 2022 Issued
Array ( [id] => 18679904 [patent_doc_number] => 20230317562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => DUAL-SIDED TERMINAL DEVICE WITH SPLIT SIGNAL AND POWER ROUTING [patent_app_type] => utility [patent_app_number] => 17/708968 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708968 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/708968
DUAL-SIDED TERMINAL DEVICE WITH SPLIT SIGNAL AND POWER ROUTING Mar 29, 2022 Pending
Array ( [id] => 19079620 [patent_doc_number] => 11949001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Multi-gate devices and fabricating the same with etch rate modulation [patent_app_type] => utility [patent_app_number] => 17/699362 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 45 [patent_no_of_words] => 11927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699362 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699362
Multi-gate devices and fabricating the same with etch rate modulation Mar 20, 2022 Issued
Array ( [id] => 17708982 [patent_doc_number] => 20220208990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => NEGATIVE-CAPACITANCE FIELD EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/699994 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699994 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699994
Negative-capacitance field effect transistor Mar 20, 2022 Issued
Array ( [id] => 19168527 [patent_doc_number] => 11984441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Integrated circuit with backside power rail and backside interconnect [patent_app_type] => utility [patent_app_number] => 17/693153 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 43 [patent_no_of_words] => 13269 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/693153
Integrated circuit with backside power rail and backside interconnect Mar 10, 2022 Issued
Array ( [id] => 18631783 [patent_doc_number] => 20230290688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/654408 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654408 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654408
Semiconductor device and method Mar 10, 2022 Issued
Array ( [id] => 18473169 [patent_doc_number] => 20230207457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => METHOD AND STRUCTURE FOR METAL TRACKS IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/690595 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690595 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/690595
Method and structure for metal tracks in semiconductor devices Mar 8, 2022 Issued
Array ( [id] => 17676972 [patent_doc_number] => 20220190139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/688236 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17688236 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/688236
Method for forming semiconductor structure Mar 6, 2022 Issued
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