Search

J. Reed Fisher

Examiner (ID: 6827)

Most Active Art Unit
3307
Art Unit(s)
3103, 2854, 3307
Total Applications
1305
Issued Applications
1002
Pending Applications
12
Abandoned Applications
291

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19146540 [patent_doc_number] => 20240145570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/408438 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12078 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408438 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408438
Method of manufacturing semiconductor devices and semiconductor devices Jan 8, 2024 Issued
Array ( [id] => 20096400 [patent_doc_number] => 20250226336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/405172 [patent_app_country] => US [patent_app_date] => 2024-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18405172 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/405172
SEMICONDUCTOR PACKAGE STRUCTURE Jan 4, 2024 Pending
Array ( [id] => 19951287 [patent_doc_number] => 12322658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Dummy fin with reduced height and method forming same [patent_app_type] => utility [patent_app_number] => 18/402245 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 38 [patent_no_of_words] => 3038 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402245 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402245
Dummy fin with reduced height and method forming same Jan 1, 2024 Issued
Array ( [id] => 19161120 [patent_doc_number] => 20240153827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => Transistor Gates and Methods of Forming Thereof [patent_app_type] => utility [patent_app_number] => 18/401866 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401866
Transistor gates and methods of forming thereof Jan 1, 2024 Issued
Array ( [id] => 19161312 [patent_doc_number] => 20240154019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => HIGH-K GATE DIELECTRIC [patent_app_type] => utility [patent_app_number] => 18/400951 [patent_app_country] => US [patent_app_date] => 2023-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400951 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/400951
High-k gate dielectric Dec 28, 2023 Issued
Array ( [id] => 19118390 [patent_doc_number] => 20240130140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => MAGNETORESISTIVE RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 18/395762 [patent_app_country] => US [patent_app_date] => 2023-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395762 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395762
Magnetoresistive random access memory Dec 25, 2023 Issued
Array ( [id] => 20792701 [patent_doc_number] => 12666633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Signal transmission device [patent_app_type] => utility [patent_app_number] => 18/394881 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 1287 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18394881 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/394881
SIGNAL TRANSMISSION DEVICE Dec 21, 2023 Issued
Array ( [id] => 19271759 [patent_doc_number] => 20240215466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MATERIAL STACK FOR MICROELECTRONIC DEVICE, A MICROELECTRONIC DEVICE THAT INTEGRATES SUCH STACK AND METHOD FOR MANUFACTURING SUCH STACK [patent_app_type] => utility [patent_app_number] => 18/393050 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18393050 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/393050
MATERIAL STACK FOR MICROELECTRONIC DEVICE, A MICROELECTRONIC DEVICE THAT INTEGRATES SUCH STACK AND METHOD FOR MANUFACTURING SUCH STACK Dec 20, 2023 Pending
Array ( [id] => 20063435 [patent_doc_number] => 20250201657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => HYBRID THERMAL INTERFACE MATERIAL WITH EMBEDDED METAL LAYER [patent_app_type] => utility [patent_app_number] => 18/545601 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545601 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/545601
HYBRID THERMAL INTERFACE MATERIAL WITH EMBEDDED METAL LAYER Dec 18, 2023 Pending
Array ( [id] => 20047139 [patent_doc_number] => 20250185361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => STACKED TRANSISTORS HAVING DUAL WORK FUNCTION GATES [patent_app_type] => utility [patent_app_number] => 18/529029 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529029 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/529029
STACKED TRANSISTORS HAVING DUAL WORK FUNCTION GATES Dec 4, 2023 Pending
Array ( [id] => 19055042 [patent_doc_number] => 20240097011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/526360 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526360 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/526360
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Nov 30, 2023 Pending
Array ( [id] => 19758114 [patent_doc_number] => 20250046679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => THROUGH VIAS AND GUARD RINGS OF SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THEREOF [patent_app_type] => utility [patent_app_number] => 18/526498 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526498 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/526498
THROUGH VIAS AND GUARD RINGS OF SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THEREOF Nov 30, 2023 Pending
Array ( [id] => 19071392 [patent_doc_number] => 20240105818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => Fin Field-Effect Transistor Device and Method of Forming the Same [patent_app_type] => utility [patent_app_number] => 18/521107 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521107 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/521107
Fin field-effect transistor device and method of forming the same Nov 27, 2023 Issued
Array ( [id] => 19055016 [patent_doc_number] => 20240096985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SEMICONDUCTOR DEVICE CONTACT STRUCTURES AND METHODS OF FABRICATING THEREOF [patent_app_type] => utility [patent_app_number] => 18/519714 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519714 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/519714
SEMICONDUCTOR DEVICE CONTACT STRUCTURES AND METHODS OF FABRICATING THEREOF Nov 26, 2023 Issued
Array ( [id] => 20113248 [patent_doc_number] => 12364003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Semiconductor devices and methods of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 18/518670 [patent_app_country] => US [patent_app_date] => 2023-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518670
Semiconductor devices and methods of manufacturing thereof Nov 23, 2023 Issued
Array ( [id] => 20113221 [patent_doc_number] => 12363976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Semiconductor devices and methods of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 18/518162 [patent_app_country] => US [patent_app_date] => 2023-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 2272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518162 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518162
Semiconductor devices and methods of manufacturing thereof Nov 21, 2023 Issued
Array ( [id] => 19038339 [patent_doc_number] => 20240088154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => BOUNDARY DESIGN FOR HIGH-VOLTAGE INTEGRATION ON HKMG TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 18/515912 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7301 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515912 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515912
Boundary design for high-voltage integration on HKMG technology Nov 20, 2023 Issued
Array ( [id] => 19038225 [patent_doc_number] => 20240088040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => MULTI-LAYER LINE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/512125 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18512125 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/512125
Multi-layer line structure Nov 16, 2023 Issued
Array ( [id] => 20013131 [patent_doc_number] => 20250151353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => SEMICONDUCTOR DEVICE AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/501960 [patent_app_country] => US [patent_app_date] => 2023-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3441 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18501960 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/501960
SEMICONDUCTOR DEVICE AND FORMATION METHOD THEREOF Nov 2, 2023 Pending
Array ( [id] => 18991092 [patent_doc_number] => 20240063061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => IN-SITU FORMATION OF METAL GATE MODULATORS [patent_app_type] => utility [patent_app_number] => 18/499650 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499650 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499650
In-situ formation of metal gate modulators Oct 31, 2023 Issued
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