Jack Cooper

Array ( [id] => 10589222 [patent_doc_number] => 09310832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Backplane clock synchronization' [patent_app_type] => utility [patent_app_number] => 13/664139 [patent_app_country] => US [patent_app_date] => 2012-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11065 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13664139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10808602 [patent_doc_number] => 20160154760 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2016-06-02 [patent_title] => 'SERVER ON A CHIP AND NODE CARDS COMPRISING ONE OR MORE OF SAME' [patent_app_type] => utility [patent_app_number] => 13/662759 [patent_app_country] => US [patent_app_date] => 2012-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13662759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10808602 [patent_doc_number] => 20160154760 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2016-06-02 [patent_title] => 'SERVER ON A CHIP AND NODE CARDS COMPRISING ONE OR MORE OF SAME' [patent_app_type] => utility [patent_app_number] => 13/662759 [patent_app_country] => US [patent_app_date] => 2012-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13662759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9006134 [patent_doc_number] => 20130227259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'CLIENT TERMINAL, OPERATING SYSTEM PROVIDING APPARATUS, AND METHODS FOR SUPPORTING MULTIPLE OPERATING SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/662892 [patent_app_country] => US [patent_app_date] => 2012-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13662892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10170772 [patent_doc_number] => 09201479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'Debug system, electronic control unit, information processing unit, semiconductor package, and transceiver circuit' [patent_app_type] => utility [patent_app_number] => 13/655312 [patent_app_country] => US [patent_app_date] => 2012-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13655312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8769410 [patent_doc_number] => 20130097447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'METHOD AND APPARATUS FOR CONTROLLING SLEEP MODE IN A PORTABLE TERMINAL' [patent_app_type] => utility [patent_app_number] => 13/653974 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4621 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13653974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9834510 [patent_doc_number] => 08943344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-27 [patent_title] => 'Power sourcing equipment for power over ethernet with low energy standby mode' [patent_app_type] => utility [patent_app_number] => 13/652504 [patent_app_country] => US [patent_app_date] => 2012-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4197 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13652504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9406634 [patent_doc_number] => 20140097886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'SYSTEMS, METHODS, AND APPARATUS FOR CONTROLLING POWER SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 13/648816 [patent_app_country] => US [patent_app_date] => 2012-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13648816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10105382 [patent_doc_number] => 09141162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-22 [patent_title] => 'Apparatus, system and method for gated power delivery to an I/O interface' [patent_app_type] => utility [patent_app_number] => 13/646468 [patent_app_country] => US [patent_app_date] => 2012-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10549 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13646468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10834720 [patent_doc_number] => 08862912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Power distribution inside cable' [patent_app_type] => utility [patent_app_number] => 13/615642 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8083 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13615642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8709963 [patent_doc_number] => 20130067252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND IC CARD USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/615301 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14990 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13615301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8699068 [patent_doc_number] => 20130061077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-07 [patent_title] => 'Power Management For A System On A Chip (SoC)' [patent_app_type] => utility [patent_app_number] => 13/611930 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2873 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13611930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8510060 [patent_doc_number] => 20120309468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'OPERATING SYSTEM (OS) VIRTUALISATION AND PROCESSOR UTILIZATION THRESHOLDS FOR MINIMIZING POWER CONSUMPTION IN MOBILE PHONES' [patent_app_type] => utility [patent_app_number] => 13/585131 [patent_app_country] => US [patent_app_date] => 2012-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6222 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13585131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8491451 [patent_doc_number] => 20120290858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'Power Control for PXI Express Controller' [patent_app_type] => utility [patent_app_number] => 13/557346 [patent_app_country] => US [patent_app_date] => 2012-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3991 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13557346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8789214 [patent_doc_number] => 20130106183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'ELECTRONIC SYSTEMS AND POWER MANAGEMENT METHODS THEREOF' [patent_app_type] => utility [patent_app_number] => 13/550631 [patent_app_country] => US [patent_app_date] => 2012-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2369 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13550631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9224966 [patent_doc_number] => 20140019741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'METHOD AND SYSTEM FOR BOOTING ELECTRONIC DEVICE FROM NAND FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 13/547045 [patent_app_country] => US [patent_app_date] => 2012-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13547045 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9688286 [patent_doc_number] => 20140245052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'Method and device for storing an item of wake-up information in users of a can bus system' [patent_app_type] => utility [patent_app_number] => 14/233945 [patent_app_country] => US [patent_app_date] => 2012-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3444 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14233945 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10150710 [patent_doc_number] => 09182999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Reintialization of a processing system from volatile memory upon resuming from a low-power state' [patent_app_type] => utility [patent_app_number] => 13/547701 [patent_app_country] => US [patent_app_date] => 2012-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5380 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13547701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8781988 [patent_doc_number] => 20130103963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'POWER SUPPLY CIRCUIT EMPLOYED IN COMPUTER FOR PERFORMING DIFFERENT STANDBY MODES' [patent_app_type] => utility [patent_app_number] => 13/461737 [patent_app_country] => US [patent_app_date] => 2012-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2972 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8672480 [patent_doc_number] => 20130047018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'POWER SUPPLY CONTROL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/461732 [patent_app_country] => US [patent_app_date] => 2012-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1998 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461732 [rel_patent_id] =>[rel_patent_doc_number] =>)